公开(公告)号：WO2006094162A3

公开(公告)日：2006-09-08

申请号：PCT/US2006/007525

申请日：2006-03-02

Applicant: APPLIED MATERIALS, INC. ,  KROPEWNICKI, Thomas J. ,  PANAGOPOULOS, Theodoros ,  GANI, Nicolas ,  PAU, Wilfred ,  SHEN, Meihua ,  HOLLAND, John P.

Inventor： KROPEWNICKI, Thomas J. ,  PANAGOPOULOS, Theodoros ,  GANI, Nicolas ,  PAU, Wilfred ,  SHEN, Meihua ,  HOLLAND, John P.

IPC: H05B31/26

Abstract: Embodiments of the invention generally provide methods for etching a substrate. In one embodiment, the method includes determining a substrate temperature target profile that corresponds to a uniform deposition rate of etch by-products on a substrate, preferentially regulating a temperature of a first portion of a substrate support relative to a second portion of the substrate support to obtain the substrate temperature target profile on the substrate, and etching the substrate on the preferentially regulated substrate support. In another embodiment, the method includes providing a substrate in a processing chamber having a selectable distribution of species within the processing chamber and a substrate support with lateral temperature control, wherein a temperature profile induced by the substrate support and a selection of species distribution comprise a control parameter set, etching a first layer of material and etching a second layer of material respectively different control parameter sets.

公开(公告)号：WO2010093567A3

公开(公告)日：2010-08-19

申请号：PCT/US2010/023386

申请日：2010-02-05

Applicant: APPLIED MATERIALS, INC. ,  SHEN, Meihua ,  SUN, Noel ,  GANI, Nicolas ,  CHEN, Han-Hsiang ,  PEI, Eric ,  ZENG, Weimin ,  LILL, Thorsten, B. ,  MITRA, Uday ,  YIEH, Ellie, Y.

Inventor： SHEN, Meihua ,  SUN, Noel ,  GANI, Nicolas ,  CHEN, Han-Hsiang ,  PEI, Eric ,  ZENG, Weimin ,  LILL, Thorsten, B. ,  MITRA, Uday ,  YIEH, Ellie, Y.

IPC: H01L21/336 ,  H01L29/78

Abstract: Methods for fabricating a semiconductor device having a lanthanum-family- based oxide layer are described. A gate stack having a lanthanum-family-based oxide layer is provided above a substrate. At least a portion of the lanthanum-family-based oxide layer is modified to form a lanthanum-family-based halide portion. The lanthanum-family-based halide portion is removed with a water vapor treatment.

公开(公告)号：WO2004012255A1

公开(公告)日：2004-02-05

申请号：PCT/US2003/021426

申请日：2003-07-03

Applicant: APPLIED MATERIALS, INC.

Inventor： ABOAMERI, Farid ,  DESHMUKH, Shashank, C. ,  SHEN, Meihua ,  CHENG, Stephanie, S. ,  GANI, Nicolas ,  LILL, Thorsten, B.

IPC: H01L21/3213

CPC classification number: H01L21/32137

Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry such as a CF 4 / CL 2 / N 2 / chemistry for a first pediod of time; and (b) etching the polysilicon utilizing a second etch chemistry such as a Hb r / CL 2 /CF 4 / He-O 2 chemistry for a second period of time.

Abstract translation: 本发明的一个实施例是一种用于在晶片或衬底上制造集成电路器件的方法，其中栅极氧化物设置在晶片或衬底之上，其上设置多晶硅层，其上设置有图案化的硬掩模， 图案化的抗反射涂层设置在其上，并且其上布置有图案化的光致抗蚀剂，该方法包括以下步骤：（a）在剥离光致抗蚀剂之前，利用第一蚀刻化学物质例如CF4 / CL2 / N2 /化学物质蚀刻多晶硅，用于 时间的第一个时期; 和（b）使用第二蚀刻化学物质（例如Hbr / CL2 / CF4 / He-O2化学物质）蚀刻多晶硅，持续第二段时间。

公开(公告)号：WO2003090351A3

公开(公告)日：2003-10-30

申请号：PCT/US2003/009937

申请日：2003-03-31

Applicant: APPLIED MATERIALS, INC.

Inventor： TODOROW, Valentin ,  HOLLAND, John ,  GANI, Nicolas

IPC: H03H7/40

Abstract: A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.

公开(公告)号：WO2003090351A2

公开(公告)日：2003-10-30

申请号：PCT/US2003/009937

申请日：2003-03-31

Applicant: APPLIED MATERIALS, INC.

Inventor： TODOROW, Valentin ,  HOLLAND, John ,  GANI, Nicolas

IPC: H03H7/40

CPC classification number: H01J37/321 ,  H01J37/32183 ,  H03H7/40

Abstract: A method and apparatus for operating a matching network within a plasma enhanced semiconductor wafer processing system that uses pulsed power to facilitate plasma processing.

Abstract translation: 一种在使用脉冲功率以促进等离子体处理的等离子体增强半导体晶片处理系统内操作匹配网络的方法和装置。