公开(公告)号：WO2018148170A1

公开(公告)日：2018-08-16

申请号：PCT/US2018/016965

申请日：2018-02-06

Applicant: APPLIED MATERIALS, INC.

Inventor： JUN, Sung Won ,  CHOPRA, Saurabh ,  KWON, Thomas Jongwan ,  PING, Er-Xuan

IPC: H01L27/11524 ,  H01L27/11529 ,  H01L21/02 ,  H01L21/28

Abstract: A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers. A method of forming a 3D NAND structure having self-aligned nanodots includes depositing alternating layers of an oxide and a nitride on a substrate; at least partially recessing the nitride layers; and forming SiGe nanodots on the nitride layers by a process including maintaining a temperature of the substrate below about 560°C; flowing a silicon epitaxy precursor into the chamber; forming a silicon epitaxial layer on the substrate at the nitride layers; flowing germanium gas into the chamber with the silicon epitaxy precursor; and forming a silicon germanium epitaxial layer on the substrate at the nitride layers.

公开(公告)号：WO2017127233A1

公开(公告)日：2017-07-27

申请号：PCT/US2017/012170

申请日：2017-01-04

Applicant: APPLIED MATERIALS, INC.

Inventor： KWON, Thomas Jongwan ,  CHENG, Rui ,  MALLICK, Abhijit Basu ,  PING, Er-Xuan ,  AHN, Jaesoo

IPC: G03F1/00 ,  G03F1/80 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

Abstract translation: 本公开的实施方式涉及用于图案化和蚀刻基板的改进的硬掩模材料和方法。 多个硬掩模可以与图案化和蚀刻工艺结合使用以实现高级器件架构。 在一个实施方式中，设置在其上设置有各种材料层的基板上的第一硬掩模和第二硬掩模。 第二硬掩模可用于在第一蚀刻工艺期间图案化第一硬掩模。 可以在第一和第二硬掩模上沉积第三硬掩模，并且可以利用第二蚀刻工艺在材料层中形成沟道。