公开(公告)号：WO2019108406A1

公开(公告)日：2019-06-06

申请号：PCT/US2018/061347

申请日：2018-11-15

Applicant: LAM RESEARCH CORPORATION

Inventor： KARIM, Ishtak ,  AGARWAL, Pulkit ,  ABEL, Joseph ,  KUMAR, Purushottam ,  LAVOIE, Adrien

IPC: H01L21/02 ,  H01J37/32

CPC classification number: H01L21/0337 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/31138 ,  H01L21/31144

Abstract: A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition of a silicon oxide based material is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition, which is complementary to the non-uniform removal of some of the carbon based deposition by the pretuning.

公开(公告)号：WO2018111289A1

公开(公告)日：2018-06-21

申请号：PCT/US2016/067069

申请日：2016-12-16

Applicant: INTEL CORPORATION

Inventor： BRISTOL, Robert L. ,  LIN, Kevin L. ,  GSTREIN, Florian

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/76885 ,  H01L23/5283

Abstract: Disclosed herein are methods for manufacturing a metallization stack including a plurality of electrically conductive interconnects by subtractive metal spacer based deposition, and related semiconductor devices. For example, in some embodiments, a method of forming a semiconductor device may include providing a pattern of sacrificial elements over an interconnect support layer, depositing an electrically conductive material on sidewalls of the sacrificial elements, and removing the sacrificial elements so that the remaining portions of the electrically conductive material form a pattern of electrically conductive elements which can serve as interconnects of a metallization stack of the semiconductor device.

公开(公告)号：WO2018094071A1

公开(公告)日：2018-05-24

申请号：PCT/US2017/062049

申请日：2017-11-16

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： FARRELL, Richard ,  MOHANTY, Nihar ,  SMITH, Jeffrey

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/022 ,  H01L21/02107 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/7688

Abstract: Techniques herein include patterning processes to prevent over-etching for various multi-patterning processes. Multi-patterning processes typically involve creation of sidewall spacers and removal of mandrels on which sidewall spacers are formed. In some patterning flows gouging of underlying layers can occurs during the various multi-patterning steps. Techniques herein include methods to prevent such gouging by using a planarization layer recessed sufficiently to removed desired materials and protect others. Such techniques can remove bi-layer mandrels without gouging underlying layers.

公开(公告)号：WO2017213817A1

公开(公告)日：2017-12-14

申请号：PCT/US2017/033242

申请日：2017-05-18

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： KO, Akiteru ,  RALEY, Angelique ,  THIBAUT, Sophie ,  NAKAMURA, Satoru ,  MOHANTY, Nihar

IPC: G03F7/20 ,  G03F1/80 ,  H01L21/027 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0337

Abstract: Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objectives.

Abstract translation: 提供一种图案化间隔物的方法，所述方法包括：在处理室中的衬底中提供初始图案化结构，所述初始图案化结构包括有机心轴和下层; 在直流叠加（DCS）等离子体处理工艺中暴露所述图案化结构，所述工艺在所述初始图案化结构上沉积第一材料层; 使用第二材料执行原子层保形沉积工艺，所述第一材料在所述原子层保形沉积工艺开始时为所述有机心轴提供保护; 执行后间隔物蚀刻心轴牵引工艺，所述工艺产生具有目标最终侧壁角度的最终图案化结构; 同时控制暴露图案化结构，原子层共形沉积工艺和后间隔物蚀刻心轴拉制工艺中的集成操作变量，以便满足目标最终侧壁角度和其他集成目标。

公开(公告)号：WO2017205136A1

公开(公告)日：2017-11-30

申请号：PCT/US2017/033051

申请日：2017-05-17

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： DEVILLIERS, Anton J. ,  MOHANTY, Nihar

IPC: H01L21/027 ,  H01L21/3065 ,  H01L21/768

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.

Abstract translation: 这里的技术使得能够整合堆叠材料和不需要腐蚀性气体进行蚀刻的多种颜色材料。 技术使得多线层可以用于自对准图案收缩，其中所有层或颜色或材料可以限于含硅材料和有机材料。 这种技术可实现5 nm后端沟槽图案化的自对准块集成，以及自对准块的所有非腐蚀性蚀刻兼容堆栈。 实施例包括使用具有相同材料但具有不同高度的线以基于材料的类型和/或材料的高度和蚀刻速率向几条线中的一条线提供蚀刻选择性。

公开(公告)号：WO2017184358A1

公开(公告)日：2017-10-26

申请号：PCT/US2017/026519

申请日：2017-04-07

Applicant: ASM IP HOLDING B.V. ,  IMEC VZW ,  ASM AMERICA, INC.

Inventor： MAES, Jan, Willem ,  KNAEPEN, Werner ,  GRONHEID, Roel ,  SINGH, Arjun

IPC: B05D3/02 ,  B05D3/04 ,  C23C8/00 ,  C23C8/06 ,  C23C16/40 ,  C23C16/44 ,  C23C16/448 ,  C23C16/52

CPC classification number: H01L21/0338 ,  G03F7/0002 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/32

Abstract: A method for forming a film with an annealing step and a deposition step is disclosed. The method comprises an annealing step for inducing self-assembly or alignment within a polymer. The method also comprises a selective deposition step in order to enable selective deposition on a polymer.

Abstract translation: 公开了一种用退火步骤和沉积步骤形成膜的方法。 该方法包括用于诱导聚合物内自组装或排列的退火步骤。 该方法还包括选择性沉积步骤，以便能够选择性沉积在聚合物上。

公开(公告)号：WO2017171737A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/024823

申请日：2016-03-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： LIANG, Di

IPC: H01L21/768 ,  H01L21/764 ,  H01L21/20

CPC classification number: H01L29/0649 ,  H01L21/02639 ,  H01L21/0337 ,  H01L21/2015 ,  H01L21/762 ,  H01L21/764 ,  H01L21/7682

Abstract: Examples herein relate to devices having substrates with selective airgap regions for mitigating defects resulting from heteroepitaxial growth of device materials. An example device may include a first semiconductor layer disposed on a substrate. The first semiconductor layer may have a window cut through a face, where etching a selective airgap region on the substrate is enabled via the window. A second semiconductor layer may be heteroepitaxially grown on the face of the first semiconductor layer so that at least a portion of the second semiconductor layer is aligned over the selective air gap region.

Abstract translation: 本文的实例涉及具有用于减轻由器件材料的异质外延生长导致的缺陷的具有选择性气隙区域的基板的器件。 示例器件可以包括设置在衬底上的第一半导体层。 第一半导体层可具有通过面切割的窗口，其中经由窗口蚀刻衬底上的选择性气隙区域。 第二半导体层可以在第一半导体层的表面上异质外延生长，使得第二半导体层的至少一部分在选择性气隙区域上对齐。

公开(公告)号：WO2017127233A1

公开(公告)日：2017-07-27

申请号：PCT/US2017/012170

申请日：2017-01-04

Applicant: APPLIED MATERIALS, INC.

Inventor： KWON, Thomas Jongwan ,  CHENG, Rui ,  MALLICK, Abhijit Basu ,  PING, Er-Xuan ,  AHN, Jaesoo

IPC: G03F1/00 ,  G03F1/80 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0338 ,  H01L21/02109 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: Implementations of the present disclosure relate to improved hardmask materials and methods for patterning and etching of substrates. A plurality of hardmasks may be utilized in combination with patterning and etching processes to enable advanced device architectures. In one implementation, a first hardmask and a second hardmask disposed on a substrate having various material layers disposed thereon. The second hardmask may be utilized to pattern the first hardmask during a first etching process. A third hardmask may be deposited over the first and second hardmasks and a second etching process may be utilized to form channels in the material layers.

Abstract translation: 本公开的实施方式涉及用于图案化和蚀刻基板的改进的硬掩模材料和方法。 多个硬掩模可以与图案化和蚀刻工艺结合使用以实现高级器件架构。 在一个实施方式中，设置在其上设置有各种材料层的基板上的第一硬掩模和第二硬掩模。 第二硬掩模可用于在第一蚀刻工艺期间图案化第一硬掩模。 可以在第一和第二硬掩模上沉积第三硬掩模，并且可以利用第二蚀刻工艺在材料层中形成沟道。

公开(公告)号：WO2017087066A1

公开(公告)日：2017-05-26

申请号：PCT/US2016/052879

申请日：2016-09-21

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： DEVILLIERS, Anton J.

IPC: H01L21/027 ,  G03F7/00 ,  H01L21/033 ,  G03F1/80

CPC classification number: H01L21/3081 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144

Abstract: Techniques disclosed herein provide a method and fabrication structure for pitch reduction for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A hardmask is positioned first on an underlying layer or layers to be etched. A pattern of alternating materials is formed on the hardmask. One or more of the alternating materials can be preferentially removed relative to other materials to uncover a portion of the hardmask layer. The hardmask and the remaining lines of alternating material together form a combined etch mask defining sub-resolution features.

Abstract translation: 本文公开的技术提供了用于产生高分辨率特征并且还用于切割子分辨率特征的间距的降低音调的方法和制造结构。 技术包括使用具有不同蚀刻特性的多种材料来选择性蚀刻特征并且在指定的地方创建切割或块。 硬掩模首先放置在待蚀刻的下层或多层上。 在硬掩模上形成交替材料的图案。 一种或多种交替材料可相对于其他材料优先移除以露出一部分硬掩模层。 硬掩模和其余的交替材料线形成了一个组合的蚀刻掩模，用于定义亚分辨率特征。

公开(公告)号：WO2017062100A1

公开(公告)日：2017-04-13

申请号：PCT/US2016/046548

申请日：2016-08-11

Applicant: APPLIED MATERIALS, INC.

Inventor： KULSHRESHTHA, Prashant Kumar ,  DUAN, Ziqing ,  NARASIMHA, Karthik Thimmavajjula ,  LEE, Kwangduk Douglas ,  KIM, Bok Hoen

IPC: H01L21/02 ,  C23C16/36 ,  C23C16/24

CPC classification number: H01L21/0338 ,  C23C16/32 ,  C23C16/505 ,  H01L21/02112 ,  H01L21/02274 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of boron-carbon films on a substrate. In one implementation, a method of processing a substrate is provided. The method comprises flowing a hydrocarbon-containing gas mixture into a processing volume of a processing chamber having a substrate positioned therein, wherein the substrate is heated to a substrate temperature from about 400 degrees Celsius to about 700 degrees Celsius, flowing a boron-containing gas mixture into the processing volume and generating an RF plasma in the processing volume to deposit a boron-carbon film on the heated substrate, wherein the boron-carbon film has an elastic modulus of from about 200 to about 400 GPa and a stress from about -100 MPa to about 100 MPa.

Abstract translation: 本公开的实施方式一般涉及集成电路的制造。 更具体地，本文所述的实施方案提供了在基底上沉积硼 - 碳膜的技术。 在一个实施方式中，提供了一种处理衬底的方法。 该方法包括将含烃气体混合物流入其中定位有基底的处理室的处理体积，其中将基底加热至约400摄氏度至约700摄氏度的基底温度，使含硼气体 混合物加入到处理体积中并在加工体积中产生RF等离子体以在加热的基底上沉积硼 - 碳膜，其中硼 - 碳膜具有约200至约400GPa的弹性模量和约 - 100MPa至约100MPa。