公开(公告)号：WO2017151192A1

公开(公告)日：2017-09-08

申请号：PCT/US2016/060467

申请日：2016-11-04

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： CHU, Fan ,  SUN, Shan ,  DEVILBISS, Alan ,  DAVENPORT, Thomas

IPC: G11C11/22 ,  H01L27/115

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  H01L27/11507 ,  H01L27/11509

Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Abstract translation: 一种包括参考产生电路的设备，所述参考产生电路经配置以产​​生用于非易失性存储器（NVM）装置的参考信号，所述参考产生电路包含第一电路，所述第一电路包括至少一个金属氧化物半导体 电容器，第一电路产生参考信号的第一信号分量，以及第二电路包括至少一个铁电电容器，第二电路产生参考信号的第二信号分量，其中第二信号分量取决于温度。 / p>

公开(公告)号：WO2017171935A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/059951

申请日：2016-11-01

Applicant: CYPRESS SEMICONDUCTOR CORPORATION

Inventor： KESHAVARZI, Ali ,  SUN, Shan ,  DAVENPORT, Thomas ,  RODGERS, Thurman John

IPC: H01L21/04 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

CPC classification number: B81B7/007 ,  B81B7/0025 ,  B81B2201/0292 ,  B81B2201/032 ,  B81B2207/07 ,  B81B2207/097 ,  H01L28/57 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic system including hydrogen barriers and copper pillars for wafer level packaging and method of fabricating the same are provided. Generally, the method includes: forming an insulating hydrogen barrier over a surface of a first substrate; exposing at least a portion of an electrical contact to a component in the first substrate by removing a portion of the insulating hydrogen barrier, the component including a material susceptible to degradation by hydrogen; forming a conducting hydrogen barrier over at least the exposed portion of the electrical contact; and forming a copper pillar over the conducting hydrogen barrier. In one embodiment, the material susceptible to degradation is lead zirconate titanate (PZT) and the microelectronic systems device is a ferroelectric random access memory including a ferroelectric capacitor with a PZT ferroelectric layer. Other embodiments are also disclosed.

Abstract translation: 提供了一种包括氢阻挡层和用于晶片级封装的铜柱的微电子系统及其制造方法。 通常，该方法包括：在第一衬底的表面上形成绝缘氢阻挡层; 通过去除绝缘氢阻挡层的一部分而将至少一部分电接触暴露于第一衬底中的部件，所述部件包括易被氢降解的材料; 在至少所述电触点的暴露部分上形成导电氢势垒; 并在导电氢屏障上形成铜柱。 在一个实施例中，易于劣化的材料是锆钛酸铅（PZT），并且微电子系统器件是包括具有PZT铁电层的铁电电容器的铁电随机存取存储器。 其他实施例也被公开。