HARDWARE SYNTHESIS USING THERMALLY AWARE SCHEDULING AND BINDING
    1.
    发明申请
    HARDWARE SYNTHESIS USING THERMALLY AWARE SCHEDULING AND BINDING 审中-公开
    使用热点调度和绑定的硬件综合

    公开(公告)号:WO2011084237A3

    公开(公告)日:2014-04-03

    申请号:PCT/US2010056526

    申请日:2010-11-12

    CPC classification number: G06F17/50 G06F17/5054 G06F2217/16

    Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

    Abstract translation: 通常使用热感知调度和绑定来描述用于硬件合成的技术。 可以生成多个版本的硬件设计,每个版本具有日程表和绑定结果的变化。 可以执行调度和绑定,使得多个版本的热分布具有在这些版本之间较远的热峰。 这些版本的热峰之间物理距离的增加可以赋予版本独特的热特性。 可以构造设计的多个版本之间的旋转时间表,使得集成电路的热分布在操作期间平衡。 可以使用线性规划框架来分析多个设计并构建热感知旋转调度和绑定。 例如,可以选择K个最有效的版本,然后可以确定在旋转期间操作每个版本的持续时间。

    SHARED MEMORIES FOR ENERGY EFFICIENT MULTI-CORE PROCESSORS
    2.
    发明申请
    SHARED MEMORIES FOR ENERGY EFFICIENT MULTI-CORE PROCESSORS 审中-公开
    能源效率高的多核处理器的共享记忆

    公开(公告)号:WO2011090673A3

    公开(公告)日:2012-04-19

    申请号:PCT/US2010061766

    申请日:2010-12-22

    CPC classification number: G06F12/084 Y02B60/1225 Y02D10/13

    Abstract: Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the shared register file is adapted to serve as a shared resource among the selected processor cores.

    Abstract translation: 这里描述了与适于共享处理器资源的多核处理器相关的技术。 示例性的多核处理器可以包括多个处理器核。 多核处理器还可以包括选择性地耦合到多个处理器核中的两个或更多个处理器核的共享寄存器文件,其中共享寄存器文件适于在所选择的处理器核间用作共享资源。

    SEMANTIC MEDICAL DEVICES
    3.
    发明申请
    SEMANTIC MEDICAL DEVICES 审中-公开
    语言医疗器械

    公开(公告)号:WO2011129817A2

    公开(公告)日:2011-10-20

    申请号:PCT/US2010030952

    申请日:2010-04-13

    Abstract: A semantic medical technology is disclosed. In various embodiments, the technology organizes an initial data collection to collect data from the one or more sensors; processes the data to obtain an initial diagnosis wherein the initial diagnosis can be a syntax diagnosis or a semantic diagnosis; identifies an organization for an additional data collection to collect additional data; analyzes the additional data to obtain a refined diagnosis; and repeats the identifying and analyzing until a stopping criterion is satisfied.

    Abstract translation: 公开了语义医学技术。 在各种实施例中,技术组织初始数据收集以从一个或多个传感器收集数据; 处理数据以获得初始诊断,其中初始诊断可以是语法诊断或语义诊断; 识别组织以获得额外的数据收集以收集附加数据; 分析附加数据以获得精确诊断; 并重复识别和分析,直到满足停止标准。

    HARDWARE BASED CRYPTOGRAPHY
    4.
    发明申请
    HARDWARE BASED CRYPTOGRAPHY 审中-公开
    基于硬件的CRYPTOGRAPHY

    公开(公告)号:WO2011016900A3

    公开(公告)日:2011-03-31

    申请号:PCT/US2010037918

    申请日:2010-06-09

    CPC classification number: H04L9/0866 H04L2209/12 H04L2209/56 H04L2209/80

    Abstract: Technologies are generally described for a hardware cryptographic unit that employs hardware public physically unclonable functions. A source computer can encrypt a message using a simulation of a hardware cryptographic unit. The encrypted message can then be sent to a destination computer. The destination computer can then use the hardware cryptographic unit to decrypt the message. The source computer can use a simulation of the hardware cryptographic unit to transform an input value into a simulation output. The simulation output can be transmitted from the source computer to the destination computer where all possible input values can be rapidly run through the hardware cryptographic unit until the output of the hardware cryptographic unit matches the simulated output. The input value that generated the matching output is now a shared secret between the source computer and destination computer without ever having been transmitted in the clear over the communication channel.

    Abstract translation: 技术通常描述为采用硬件公共物理不可克隆功能的硬件加密单元。 源计算机可以使用硬件加密单元的模拟来加密消息。 然后可以将加密的消息发送到目的地计算机。 目的地计算机然后可以使用硬件加密单元来解密消息。 源计算机可以使用硬件加密单元的模拟来将输入值转换成模拟输出。 仿真输出可以从源计算机传输到目标计算机,其中所有可能的输入值可以通过硬件加密单元快速运行,直到硬件加密单元的输出与模拟输出匹配。 生成匹配输出的输入值现在是源计算机和目的地计算机之间的共享秘密,而无需通过通信通道清除传输。

    HETEROGENEOUS MULTICORE PROCESSOR WITH GRAPHENE-BASED TRANSISTORS
    6.
    发明申请
    HETEROGENEOUS MULTICORE PROCESSOR WITH GRAPHENE-BASED TRANSISTORS 审中-公开
    具有基于石墨的晶体管的异质多元处理器

    公开(公告)号:WO2015023277A3

    公开(公告)日:2016-07-07

    申请号:PCT/US2013055025

    申请日:2013-08-15

    Abstract: Techniques described herein generally include methods and systems related to the use of processors that include graphene-containing computing elements while minimizing or otherwise reducing the effects of high leakage energy associated with graphene computing elements. Furthermore, embodiments of the present disclosure provide systems and methods for scheduling instructions for processing by a chip multiprocessor that includes graphene-containing computing elements arranged in multiple processor groups.

    Abstract translation: 本文描述的技术通常包括与包括含石墨烯计算元件的处理器的使用相关的方法和系统,同时最小化或以其他方式减少与石墨烯计算元件相关联的高泄漏能量的影响。 此外,本公开的实施例提供了用于调度用于由芯片多处理器处理的指令的系统和方法,所述芯片多处理器包括布置在多个处理器组中的含石墨烯的计算元件。

    YIELD OPTIMIZATION OF PROCESSOR WITH GRAPHENE-BASED TRANSISTORS
    7.
    发明申请
    YIELD OPTIMIZATION OF PROCESSOR WITH GRAPHENE-BASED TRANSISTORS 审中-公开
    基于石墨的晶体管的处理器的优化优化

    公开(公告)号:WO2015023276A3

    公开(公告)日:2016-07-07

    申请号:PCT/US2013055024

    申请日:2013-08-15

    Abstract: Techniques described herein generally include methods and systems related to the selection of a combination of graphene an non-graphene transistors in an IC design. To reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. To limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized.

    Abstract translation: 本文描述的技术通常包括与IC设计中的非石墨烯晶体管的石墨烯组合的选择相关的方法和系统。 为了减少由石墨烯晶体管引起的泄漏能量的增加,所选择的非石墨烯晶体管可以用IC设计中的石墨烯晶体管代替,而其它非石墨烯晶体管可以保留在IC设计中。 为了限制IC设计中的石墨烯晶体管的数量,石墨烯晶体管可以主要在IC设计中的位置处替代非石墨烯晶体,其中可以实现显着的延迟效益。

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