Abstract:
Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
Abstract:
Technologies are described herein related to multi-core processors that are adapted to share processor resources. An example multi-core processor can include a plurality of processor cores. The multi-core processor further can include a shared register file selectively coupled to two or more of the plurality of processor cores, where the shared register file is adapted to serve as a shared resource among the selected processor cores.
Abstract:
A semantic medical technology is disclosed. In various embodiments, the technology organizes an initial data collection to collect data from the one or more sensors; processes the data to obtain an initial diagnosis wherein the initial diagnosis can be a syntax diagnosis or a semantic diagnosis; identifies an organization for an additional data collection to collect additional data; analyzes the additional data to obtain a refined diagnosis; and repeats the identifying and analyzing until a stopping criterion is satisfied.
Abstract:
Technologies are generally described for a hardware cryptographic unit that employs hardware public physically unclonable functions. A source computer can encrypt a message using a simulation of a hardware cryptographic unit. The encrypted message can then be sent to a destination computer. The destination computer can then use the hardware cryptographic unit to decrypt the message. The source computer can use a simulation of the hardware cryptographic unit to transform an input value into a simulation output. The simulation output can be transmitted from the source computer to the destination computer where all possible input values can be rapidly run through the hardware cryptographic unit until the output of the hardware cryptographic unit matches the simulated output. The input value that generated the matching output is now a shared secret between the source computer and destination computer without ever having been transmitted in the clear over the communication channel.
Abstract:
A sensor system and method configured to take multiple channels of sensors, and based on context and user behavior reflected in the signals, identifies specified channels for sensing according to a sensing policy. The sensing policy is used to reduce the amount of data sampled, such that it is possible to reconstruct the values of the non sampled sensors efficiently. The sensing policy is influenced by user and system's behavior and can be assigned either offline or in real time.
Abstract:
Techniques described herein generally include methods and systems related to the use of processors that include graphene-containing computing elements while minimizing or otherwise reducing the effects of high leakage energy associated with graphene computing elements. Furthermore, embodiments of the present disclosure provide systems and methods for scheduling instructions for processing by a chip multiprocessor that includes graphene-containing computing elements arranged in multiple processor groups.
Abstract:
Techniques described herein generally include methods and systems related to the selection of a combination of graphene an non-graphene transistors in an IC design. To reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. To limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized.