公开(公告)号：WO2008014033A2

公开(公告)日：2008-01-31

申请号：PCT/US2007/068100

申请日：2007-05-03

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHOY, Jon S. ,  AKHTER, Tahmina

Inventor： CHOY, Jon S. ,  AKHTER, Tahmina

IPC: G11C5/14

CPC classification number: G11C29/02 ,  G11C7/04 ,  G11C7/062 ,  G11C7/14 ,  G11C16/28 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/063

Abstract: A memory (12) includes a plurality of memory cells (12), a sense amplifier (18) coupled to at least one of the plurality of memory cells, a temperature dependent current generator (26) comprising a plurality of selectable temperature dependent current sources (52-62) for generating a temperature dependent current, a temperature independent current generator (28) comprising a plurality of selectable temperature independent current sources (70, 72, 74) for generating a temperature independent current, and a summer (30) coupled to the temperature dependent current generator (26) and the temperature independent current generator (28) for combining the temperature dependent current and the temperature independent current to generate a reference current for use by the sense amplifier (18). A temperature coefficient of the reference current is approximately a same as a temperature coefficient of a memory cell current of at least one of the plurality of memory cells.

Abstract translation: 存储器（12）包括多个存储器单元（12），耦合到所述多个存储器单元中的至少一个存储器单元的读出放大器（18），温度依赖性电流发生器（26），所述温度依赖性电流发生器 用于产生温度依赖电流的多个可选择温度依赖电流源（52-62），包括多个可选择温度独立电流源（70,72,74）的独立于温度的电流发生器（28），用于产生温度独立电流 ，以及耦合到温度依赖电流发生器（26）和温度独立电流发生器（28）的加法器（30），用于组合温度依赖电流和温度独立电流以生成供读出放大器（18）使用的参考电流 ）。 参考电流的温度系数与多个存储器单元中的至少一个存储器单元的存储器单元电流的温度系数大致相同。

公开(公告)号：WO2014175896A1

公开(公告)日：2014-10-30

申请号：PCT/US2013/038435

申请日：2013-04-26

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  CHRUDIMSKY, David W. ,  SANJEEVARAO, Padmaraj ,  CHOY, Jon S.

Inventor： CHRUDIMSKY, David W. ,  SANJEEVARAO, Padmaraj ,  CHOY, Jon S.

IPC: G11C7/10 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C5/145 ,  G11C7/20 ,  G11C8/08 ,  G11C2207/2209

Abstract: A memory including a plurality of word line drivers and two charge pumps. During an initialization mode, a first charge pump provides a supply voltage to a first set of word line drivers and a second charge pump provides a voltage to a second set of word line drivers. During a normal read operation, the second charge pump supplies a supply voltage to the word line driver used for the read operation. During a normal mode write operation, the first charge pump supplies a supply voltage to the word line driver being used for the write operation.

Abstract translation: 包括多个字线驱动器和两个电荷泵的存储器。 在初始化模式期间，第一电荷泵向第一组字线驱动器提供电源电压，而第二电荷泵向第二组字线驱动器提供电压。 在正常读取操作期间，第二电荷泵向用于读取操作的字线驱动器提供电源电压。 在正常模式写入操作期间，第一电荷泵向用于写入操作的字线驱动器提供电源电压。

公开(公告)号：WO2009017889A1

公开(公告)日：2009-02-05

申请号：PCT/US2008/067222

申请日：2008-06-17

Applicant: FREESCALE SEMICONDUCTOR INC. ,  EGUCHI, Richard K. ,  CHOY, Jon S.

Inventor： EGUCHI, Richard K. ,  CHOY, Jon S.

IPC: G11C16/04 ,  G11C11/34 ,  G11C7/00

CPC classification number: G11C16/344 ,  G11C16/3409

Abstract: An erase operation in a non-volatile memory (10) includes selecting a block (14, 16, or 18) on which to perform an erase operation, erasing the selected block≠ receiving test data corresponding to the selected block, determining a soft program verify voltage level based on the test data, and soft programming the erased selected block using the soft program verify voltage level. A non-volatile memory (10) includes a plurality of blocks, a test block (20) which stores test data corresponding to each of the plurality of blocks, and a flash control (30) coupled to the plurality of blocks and the test block, the flash control determining a soft program verify voltage level for a particular block of the plurality of blocks based on the test data for the particular block when the particular block is being soft programmed.

Abstract translation: 在非易失性存储器（10）中的擦除操作包括选择在其上执行擦除操作的块（14,16或18），擦除所选择的块 接收对应于所选块的测试数据，基于测试数据确定软程序验证电压电平，以及使用软程序验证电压电平对所擦除的所选块进行软编程。 非易失性存储器（10）包括多个块，存储对应于多个块中的每一个的测试数据的测试块（20）和耦合到多个块的闪存控制（30）和测试块 当所述特定块被软编程时，所述闪光控制基于所述特定块的测试数据确定所述多个块的特定块的软程序验证电压电平。

公开(公告)号：WO2009020718A1

公开(公告)日：2009-02-12

申请号：PCT/US2008/068091

申请日：2008-06-25

Applicant: FREESCALE SEMICONDUCTOR INC. ,  CHOY, Jon S. ,  WANG, Yanzhuo

Inventor： CHOY, Jon S. ,  WANG, Yanzhuo

IPC: G11C7/20 ,  G11C7/24 ,  G11C16/30

CPC classification number: G11C5/147 ,  G11C5/143 ,  G11C5/145

Abstract: A circuit and method reduces disturb in a memory array (12) resulting from one of two supply voltages dropping below a predetermined value. Memory control logic (22) is operated using a logic power domain. Higher voltages than that of the logic power domain are generated in response to an oscillator (18) oscillating. The higher voltages are used to operate the memory array (12). Operation of the oscillator (18) is controlled with the memory control logic (22) when the logic power domain is at least at a first level or value. The oscillator (18) is disabled when the logic power domain is below the first level. The disabling of the oscillator (18) has the effect of preventing generation of the higher voltages. This facilitates preventing the higher voltages from reaching the memory array (12) when they may not be properly controlled.

Abstract translation: 电路和方法减少由两个电源电压之一下降到预定值以下的存储器阵列（12）中的干扰。 存储器控制逻辑（22）使用逻辑电源域进行操作。 响应于振荡器（18）振荡而产生比逻辑功率域的电压更高的电压。 较高的电压用于操作存储器阵列（12）。 当逻辑功率域至少处于第一级或值时，通过存储器控制逻辑（22）来控制振荡器（18）的操作。 当逻辑电源域低于第一电平时，振荡器（18）被禁止。 振荡器（18）的禁用具有防止产生较高电压的效果。 这有助于防止当它们可能不被适当地控制时更高的电压到达存储器阵列（12）。

公开(公告)号：WO2007100939A3

公开(公告)日：2007-09-07

申请号：PCT/US2007/060844

申请日：2007-01-22

Applicant: FREESCALE SEMICONDUCTOR INC. ,  EGUCHI, Richard K. ,  CHOY, Jon S.

Inventor： EGUCHI, Richard K. ,  CHOY, Jon S.

IPC: G11C11/34

Abstract: A non-volatile memory (12) can have multiple blocks (14, 16, 18) erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory (12) because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block (20) of the non-volatile memory (12) that is inaccessible to the user.