公开(公告)号：WO2023280669A2

公开(公告)日：2023-01-12

申请号：PCT/EP2022/068021

申请日：2022-06-30

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： YAGHOUBI, Farhad ,  ZHANG, Biwei ,  BEYER, Harald

IPC: H01L23/488 ,  H01L23/49 ,  H01L21/60 ,  H01L25/07

Abstract: A power module (10) is provided which comprises a substrate (2), an electronic component (3) and an electrical connection (4), wherein the power module further comprises a first connection layer (5B) and a second connection layer (5C). The substrate (2) has a first metallization layer (21) and a second metallization layer (22) spatially separated from the first metallization layer (21) by a separating trench (2T). The first connection layer (5B) is formed along a vertical direction between the substrate (2) and the electronic component (3). The electronic component (3) is a semiconductor chip and is electrically and thermally connected to the first metallization layer (21) by the first connection layer (5B) being a patterned sintered connection layer which forms a sintered connection between the substrate (2) and the electronic component (3). In top view, an area (50) of the sintered connection is partly covered by a sintering material, wherein not-covered subregions (50U) are bordered by one or several outer edges (50E) of the area (50). A ratio of surfaces of the not-covered subregions (50U) to the respective area (50) of the sintered connection is between 10 % and 75 %, inclusive. The electrical connection (4) is electrically connected to the electronic component (3) by the second connection layer (5C) being another patterned sintered connection layer. Moreover, a method for producing such a power module (10) is provided.

公开(公告)号：WO2022258297A1

公开(公告)日：2022-12-15

申请号：PCT/EP2022/062915

申请日：2022-05-12

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： KICIN, Slavo ,  SCHROEDER, Arne ,  YAGHOUBI, Farhad

IPC: H01L25/07 ,  H01L23/64 ,  H01L23/538 ,  H01L23/373 ,  H03K17/12 ,  H03K17/16

Abstract: The disclosure relates to a power semiconductor module (1) comprising at least two groups (2, 3; 31, 32, 33, 34) of semiconductor switches (4) connected in parallel, the semiconductor switches (4) of each group being connected in parallel within the group (2, 3; 31, 32, 33, 34), a module gate contact (5), a group gate contact (6,7) for each group, a first branching point (8) connected to the module gate contact (5) and to the group gate contacts (6, 7), a gate path between the module gate contact (5) and the first branching point (8) being shared for the at least two groups of semiconductor switches (2, 3; 31, 32, 33, 34), and a compensation structure (9; 39) in a connection path between the first branching point (8) and gate terminals (10) of the semiconductor switches (4) of at least one group (3) of semiconductor switches (4) for increasing the inductance of said connection path.