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    TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EMPLOYING DIFFERENT SEMICONDUCTOR MATERIAL
    3.
    发明申请
    TUNNELING TRANSISTORS INCLUDING SOURCE/DRAIN REGIONS EMPLOYING DIFFERENT SEMICONDUCTOR MATERIAL 审中-公开
    包括使用不同半导体材料的源/漏区的隧道晶体管

    公开(公告)号：WO2018063310A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054724

    申请日：2016-09-30

    申请人： INTEL CORPORATION

    发明人： GLASS, Glenn A. ,  MURTHY, Anand S. ,  YOUNG, Ian A. ,  AVCI, Uygar E.

    IPC分类号： H01L29/78 ,  H01L29/73 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

    CPC分类号： H01L29/7391 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66356 ,  H01L29/775 ,  H01L29/785

    摘要： Techniques are disclosed for forming tunneling transistors including source and drain (S/D) regions employing different material. Using material bandgap engineering, the techniques enhance the ability of transistor devices that employ quantum tunneling, such as tunnel field-effect transistors (TFETs) and Fermi filter FETs (FFFETs), to resist off-state leakage currents from source to drain (through the channel) and from source to ground/substrate. The material bandgap engineering can incorporate a material-based band offset component to control off-state leakage. Such a band offset can expand upon the limited energy band offset achievable using conventional material configurations (e.g., single composition material configurations), because with such conventional material configurations, above a threshold doping concentration, there is no additional decrease in leakage current for a given source to drain voltage at fixed dimensions. For example, increasing the band offset can increase the barrier that carriers must overcome to reach the channel region, thereby reducing off-state leakage.

    摘要翻译： 公开了用于形成包括采用不同材料的源极和漏极（S / D）区域的隧穿晶体管的技术。 利用材料带隙工程技术，这些技术增强了采用量子隧穿技术的晶体管器件（如隧道场效应晶体管（TFET）和费米滤波器FET（FFFET））的能力，可以抵抗从源极到漏极的截止状态泄漏电流（通过 通道）以及从源到地/衬底。 材料带隙工程可以结合基于材料的带偏移分量来控制关态漏电。 这种频带偏移可以在利用常规材料配置（例如，单一组合材料配置）可实现的有限能带偏移时扩大，因为对于给定的给定阈值掺杂浓度以上的这种常规材料配置，不存在额外的漏电流降低 源以固定尺寸的漏极电压。 例如，增加频带偏移可以增加载波必须克服才能到达信道区域的屏障，从而减少关闭状态泄漏。

    InN TUNNEL JUNCTION CONTACTS FOR P-CHANNEL GaN
    4.
    发明申请
    InN TUNNEL JUNCTION CONTACTS FOR P-CHANNEL GaN 审中-公开
    InN隧道结接点用于P沟道GaN

    公开(公告)号：WO2018063224A1

    公开(公告)日：2018-04-05

    申请号：PCT/US2016/054368

    申请日：2016-09-29

    申请人： INTEL CORPORATION

    发明人： RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  THEN, Han Wui

    IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/66

    CPC分类号： H01L29/2003 ,  H01L29/0847 ,  H01L29/0895 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545

    摘要： Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

    摘要翻译： 公开了用于半导体制造的方法和设备。 示例装置包括氮化镓（GaN）衬底; 位于GaN衬底上的p型GaN区域; 位于所述GaN衬底上并且与所述p型GaN区共享界面的p型氮化铟（InN）区; 和位于GaN衬底上并且与p型InN区共享界面的n型氮化铟镓（InGaN）区。

    SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE STRUCTURES
    9.
    发明申请
    SEMICONDUCTOR DEVICES WITH RAISED DOPED CRYSTALLINE STRUCTURES 审中-公开
    具有放大结晶结构的半导体器件

    公开(公告)号：WO2016186654A1

    公开(公告)日：2016-11-24

    申请号：PCT/US2015/031542

    申请日：2015-05-19

    申请人： INTEL CORPORATION

    发明人： RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  GARDNER, Sanaz K. ,  SUNG, Seung Hoon ,  THEN, Han Wui ,  CHAU, Robert S.

    IPC分类号： H01L29/778

    CPC分类号： H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

    摘要： Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

    摘要翻译： 描述了包括从器件层延伸的升高或凸起的掺杂晶体结构的半导体器件。 在实施例中，III-N晶体管包括在栅极堆叠的任一侧上的凸起的结晶n +掺杂的源极/漏极结构。 在实施例中，使用非晶材料来限制多晶源/漏极材料的生长，允许高质量的源极/漏极掺杂晶体从未损坏的区域生长并且横向膨胀以形成具有二度电子气体的低电阻界面（ 2DEG）形成在器件层内。 在一些实施例中，可能产生竞争性多晶过度生长的损坏的GaN的区域在开始升高的源极/漏极生长之前被无定形材料覆盖。