公开(公告)号：WO2018182697A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025436

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： ATANASOV, Sarah ,  SURI, Satyarth ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  KUO, Charles C.

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device, includes an MTJ material layer stack having an uppermost surface, a lowermost surface, and a sidewall ending from the uppermost surface to the lowermost surface. The MTJ material stack includes a fixed magnet, a tunnel barrier disposed above the fixed magnet, a free magnet disposed on the tunnel barrier and a passivation layer disposed laterally adjacent to the sidewall of the MTJ material stack. The passivation layer extends only partially along the sidewall between the uppermost surface of the MTJ material layer stack and the lowermost surface of the MTJ material stack.

公开(公告)号：WO2019005082A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040136

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： KUO, Charles C. ,  ATANASOV, Sarah ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  SURI, Satyarth

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: MTJ material stacks including one or more material layers that have outdiffused one or more dopants through a layer sidewall edge, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. A free magnet layer or fixed magnet layer may include a dopant, such as boron. A liner layer may be deposited over an MTJ stack, for example in close proximity to the edge of at least one of the fixed or free magnet layers. During a thermal anneal, a dopant, such as boron, may be gettered by the liner. Dopant gettering by the liner may facilitate changes with in the MTJ stack, such as development of perpendicular magnetic anisotropy within a magnet layer. Following dopant gettering, the liner may be retained, or at least partially removed as sacrificial.

公开(公告)号：WO2021194597A1

公开(公告)日：2021-09-30

申请号：PCT/US2020/066985

申请日：2020-12-23

Applicant: INTEL CORPORATION

Inventor： SHARMA, Abhishek ,  SATO, Noriyuki ,  ATANASOV, Sarah ,  SUMBUL, Huseyin Ekin ,  CHEN, Gregory K. ,  KNAG, Phil ,  KRISHNAMURTHY, Ram ,  YOO, Hui Jae ,  LE, Van H.

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2211/4066 ,  G11C5/025 ,  G11C7/1078 ,  H01L27/10844 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1266 ,  H01L28/90

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：WO2019005128A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040405

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： KUO, Charles C. ,  ATANASOV, Sarah ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P.

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/12

Abstract: MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. Nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact during device operation. With such an architecture lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). A nano- contact may be fabricated with a spacer-based multi-patterning technique.

公开(公告)号：WO2019005156A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040493

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

Inventor： O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  DOCZY, Mark L. ,  SURI, Satyarth ,  ATANASOV, Sarah

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A spin orbit torque (SOT) memory device includes a spin orbit torque electrode disposed in a dielectric layer above a substrate and a magnetic tunnel junction (MTJ) device disposed on a portion of the spin orbit torque electrode. The spin orbit torque electrode has an uppermost is 10-20 times larger than the MTJ device. The MTJ device includes a free layer disposed on the spin orbit torque electrode, a tunnel barrier such as an MgO disposed on the free layer and a fixed layer disposed on the tunnel barrier.

公开(公告)号：WO2019005127A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040403

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： KUO, Charles C. ,  ATANASOV, Sarah ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  O'BRIEN, Kevin P.

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

Abstract: MTJ material stacks including one or more nano-contact, MTJ devices employing such stacks, and computing platforms employing such MTJ devices. Nano-contacts having lateral dimensions smaller than the lateral dimensions of a free magnet layer may convey a high current density into the free magnetic layer at their point(s) of contact during device operation. With such an architecture lower write currents and/or reduced switching times may be achieved for an MTJ device having a given free magnet area (footprint). A nano-contact may be fabricated as a conductive spacer self-aligned with a sidewall of topography created in a dielectric layer.

公开(公告)号：WO2019005075A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040037

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： KUO, Charles ,  ATANASOV, Sarah ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin

IPC: H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  H01L43/12

Abstract: Apparatuses including a non-conformal sidewall material layer adjacent to a sloped sidewall magnetic tunnel junction stack having a fixed magnet layer and a free magnet layer separated by a barrier layer and a terminal electrode, systems incorporating such apparatuses, and methods for forming them are discussed.

公开(公告)号：WO2018009155A1

公开(公告)日：2018-01-11

申请号：PCT/US2016/040888

申请日：2016-07-02

Applicant: INTEL CORPORATION

Inventor： SHAH, Uday ,  PILLARISETTY, Ravi ,  KARPOV, Elijah V. ,  MUKHERJEE, Niloy ,  CLARKE, James S. ,  ATANASOV, Sarah ,  MAJHI, Prashant

IPC: H01L45/00

Abstract: Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described. In an example, an RRAM cell includes a conductive interconnect disposed in a first dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect and includes a bottom electrode layer formed above the conductive interconnect. An oxygen exchange metal layer is formed on the bottom electrode layer. A switching layer is formed on the oxygen exchange metal layer. A first dielectric hardmask layer is formed on the switching layer and includes an opening. A portion of a top electrode layer is formed in the opening, on the oxygen exchange metal layer. A top electrode fill metal layer is formed on the top electrode layer.

Abstract translation: 描述了具有底部氧交换层的电阻随机存取存储器（RRAM）器件及其制造方法。 在一个示例中，RRAM单元包括设置在衬底上方的第一电介质层中的导电互连。 RRAM器件耦合到导电互连并且包括形成在导电互连上方的底部电极层。 氧气交换金属层形成在底部电极层上。 在氧交换金属层上形成开关层。 第一电介质硬掩模层形成在开关层上并且包括开口。 顶部电极层的一部分形成在氧气交换金属层上的开口中。 顶部电极填充金属层形成在顶部电极层上。