公开(公告)号：WO2018182642A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025147

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： DOCZY, Mark L. ,  DOYLE, Brian S. ,  WIEGAND, Christopher J. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  KUO, Charles C. ,  TSENG, Ricky J. ,  OUELLETTE, Daniel G. ,  RAHMAN, MD Tofizur ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  GOLONZKA, Oleg ,  GHANI, Tahir

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier layer between the free and fixed layers; the tunnel barrier layer directly contacting a first side of the free layer; and a first side of an oxide layer directly contacting a second side of the free layer; and a first side of an additional layer directly contacting a second side of the oxide layer; wherein the oxide layer includes a metal and the additional layer includes the metal. Other embodiments are described herein.

公开(公告)号：WO2018063389A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054985

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： AHMED, Khaled ,  TSENG, Ricky J.

IPC: H01L33/48 ,  H01L33/58 ,  H01L33/36 ,  H01L33/02

CPC classification number: H01L33/20 ,  H01L33/42 ,  H01L33/52

Abstract: Disclosed herein are devices incorporating micro light emitting diodes with angled or curved geometries, and methods of producing the same. In one implementation, an apparatus comprises a substrate and a micro light emitting diode formed above the substrate. The micro LED comprises an upper surface, a lower surface, and a sidewall. A geometry of the micro LED may be selected from an angled sidewall geometry, a lens-shaped geometry, or a combination thereof.

Abstract translation: 这里公开的是结合具有成角度或弯曲几何形状的微型发光二极管的器件及其制造方法。 在一个实施方式中，装置包括衬底和形成在衬底上方的微发光二极管。 微型LED包括上表面，下表面和侧壁。 微型LED的几何形状可以从成角度的侧壁几何形状，透镜形状的几何形状或它们的组合中选择。

公开(公告)号：WO2017171812A1

公开(公告)日：2017-10-05

申请号：PCT/US2016/025393

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： CHANG, Peter L. ,  TSENG, Ricky J. ,  BAN, Ibrahim ,  HUA, Fay ,  GARDNER, Sanaz K.

IPC: H01L33/04 ,  H01L33/06 ,  H01L33/58 ,  H01L33/36 ,  H01L33/44

Abstract: Methods of manufacturing, and devices including, a light emitting diode (LED). The LED includes a first electrode, a first epitaxial layer located adjacent the first electrode and having a contact surface, a second electrode, and a second epitaxial layer located adjacent the second electrode. A quantum well may be located between the first epitaxial layer and the second epitaxial layer of the LED. The quantum well may include a planar surface located adjacent the contact surface of the first epitaxial layer, and the planar surface may have a larger surface area than the contact surface of the first epitaxial layer

Abstract translation: 制造方法以及包括发光二极管（LED）的装置。 LED包括第一电极，与第一电极相邻并具有接触表面的第一外延层，第二电极和位于第二电极附近的第二外延层。 量子阱可以位于LED的第一外延层和第二外延层之间。 量子阱可以包括位于第一外延层的接触表面附近的平坦表面，并且平坦表面可以具有比第一外延层的接触表面更大的表面积，

公开(公告)号：WO2018125122A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069139

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： DOYLE, Brian S. ,  OGUZ, Kaan ,  TSENG, Ricky J. ,  O'BRIEN, Kevin P.

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L27/11585

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

公开(公告)号：WO2018125118A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069121

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： DOYLE, Brian S. ,  O'BRIEN, Kevin P. ,  TSENG, Ricky J. ,  OGUZ, Kaan

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11585

Abstract: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) formed in the back end of the IC structure. The disclosed back-end FE-FET devices may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end, and in some cases, an alloy of doped or undoped transition metal oxides may be used as the ferroelectric material. The disclosed back-end FE-FET devices may be able to provide comparable or improved ferroelectric performance relative to FE-FET devices formed during front-end processing. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices may also free up floor space in the front-end, thereby providing space for additional devices in the front-end.