公开(公告)号：WO2007078840A1

公开(公告)日：2007-07-12

申请号：PCT/US2006/047733

申请日：2006-12-14

Applicant: INTEL CORPORATION ,  HANNAH, Eric, C. ,  TENNENHOUSE, David

Inventor： HANNAH, Eric, C. ,  TENNENHOUSE, David

IPC: H03K19/08 ,  H03K19/173 ,  G06F7/501

CPC classification number: H03K19/0813 ,  H03K19/094

Abstract: Embodiments utilize analog sub-threshold circuits to perform Boolean logic and soft-gate logic. These analog circuits may be grouped into configurable logic blocks that are locally asynchronous, but block-level synchronous. The Boolean logic, or function, performed by these blocks may be configured by programming bits. Other embodiments are described and claimed.

Abstract translation: 实施例利用模拟子阈值电路来执行布尔逻辑和软门逻辑。 这些模拟电路可以被分组为本地异步但是块级同步的可配置逻辑块。 由这些块执行的布尔逻辑或功能可以通过编程位来配置。 描述和要求保护其他实施例。

公开(公告)号：WO2008088505A1

公开(公告)日：2008-07-24

申请号：PCT/US2007/025068

申请日：2007-12-06

Applicant: INTEL CORPORATION ,  HANNAH, Eric, C. ,  MORRISS, Jeff, C.

Inventor： HANNAH, Eric, C. ,  MORRISS, Jeff, C.

IPC: H01P3/08 ,  H05K1/02

CPC classification number: H01P3/08 ,  H05K1/024 ,  H05K1/0254 ,  H05K1/167 ,  H05K2201/0738 ,  H05K2201/10196

Abstract: In some embodiments, an apparatus includes a printed circuit board substrate, a copper signal line disposed on the printed circuit board substrate, and a nonlinear transmission structure coupled to the copper signal line, wherein the nonlinear transmission structure is configured to sharpen a wavefront of a high speed signal pulse on the copper signal line. In some embodiments, the nonlinear transmission structure may include a voltage dependent dielectric layer on the printed circuit board substrate. In some embodiments, the voltage dependent dielectric layer may include a plurality of varactors positioned at a receiving end of the signal line.

Abstract translation: 在一些实施例中，一种装置包括印刷电路板基板，布置在印刷电路板基板上的铜信号线和耦合到铜信号线的非线性传输结构，其中非线性传输结构被配置为锐化波前的波前 铜信号线上的高速信号脉冲。 在一些实施例中，非线性传输结构可以包括印刷电路板衬底上的电压依赖介电层。 在一些实施例中，电压依赖介质层可以包括位于信号线的接收端的多个变容二极管。

公开(公告)号：WO2007001307A2

公开(公告)日：2007-01-04

申请号：PCT/US2005/023252

申请日：2005-06-29

Applicant: INTEL CORPORATION ,  HANNAH, Eric, C.

Inventor： HANNAH, Eric, C.

IPC: G01T1/00 ,  H01L31/00 ,  G06F11/00

CPC classification number: G06F11/1405 ,  H01L23/556 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, a cosmic ray detector includes a cantilever with a first tip. The detector also includes a second tip and circuitry to provide a signal indicative of a distance between the first and second tips being such as would be caused by a cosmic ray interaction event. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，宇宙射线检测器包括具有第一尖端的悬臂。 检测器还包括第二尖端和电路，以提供指示第一尖端和第二尖端之间的距离的信号，例如这将由宇宙线交互事件引起。 描述并要求保护其他实施例。

公开(公告)号：WO2011123135A1

公开(公告)日：2011-10-06

申请号：PCT/US2010/029821

申请日：2010-04-02

Applicant: INTEL CORPORATION ,  GARDNER, Donald, S. ,  HANNAH, Eric, C. ,  CHEN, Rong ,  GUSTAFSON, John, L.

Inventor： GARDNER, Donald, S. ,  HANNAH, Eric, C. ,  CHEN, Rong ,  GUSTAFSON, John, L.

IPC: H01G4/005

CPC classification number: H01G11/86 ,  H01G2/02 ,  H01G9/048 ,  H01G11/24 ,  H01G11/26 ,  H01G11/36 ,  H01G11/52 ,  H01G11/54 ,  H01L28/82 ,  Y02E60/13

Abstract: In one embodiment a charge storage device includes first (110) and second (120) electrically conductive structures separated from each other by a separator (130). At least one of the first and second electrically conductive structures includes a porous structure containing multiple channels (111, 121). Each one of the channels has an opening (112, 122) to a surface (115, 125) of the porous structure. In another embodiment the charge storage device includes multiple nanostructures (610) and an electrolyte (650) in physical contact with at least some of the nanostructures. A material (615) having a dielectric constant of at least 3.9 may be located between the electrolyte and the nanostructures.

Abstract translation: 在一个实施例中，电荷存储装置包括通过分离器（130）彼此分离的第一（110）和第二（120）导电结构。 第一和第二导电结构中的至少一个包括包含多个通道（111,121）的多孔结构。 每个通道具有到多孔结构的表面（115,125）的开口（112,122）。 在另一个实施方案中，电荷存储装置包括与至少一些纳米结构物理接触的多个纳米结构（610）和电解质（650）。 具有至少3.9的介电常数的材料（615）可以位于电解质和纳米结构之间。

公开(公告)号：WO2007064540A3

公开(公告)日：2007-06-07

申请号：PCT/US2006/045141

申请日：2006-11-20

Applicant: INTEL CORPORATION ,  HANNAH, Eric, C.

Inventor： HANNAH, Eric, C.

IPC: G11B9/00 ,  G11C13/02

Abstract: Apparatus, systems and methods for implementing molecular quantum memory are disclosed. In one implementation, a source of polarized electrons (104) and a source of oppositely polarized electrons (106) maybe selectively coupled to at least one probe tip (117, 119) of a probe assembly. The at least one probe tip may, in turn, be electrically coupled to a molecule so that information may be written to the molecule using a time- varying polarized electron current selectively derived from the polarized electron current sources.

公开(公告)号：WO2006012166A2

公开(公告)日：2006-02-02

申请号：PCT/US2005/022148

申请日：2005-06-22

Applicant: INTEL CORPORATION ,  HANNAH, Eric, C.

Inventor： HANNAH, Eric, C.

CPC classification number: G06F11/00

Abstract: In some embodiments, a system includes a cosmic ray detector to detect cosmic rays and to generate cosmic ray detection signals indicative of the detected cosmic rays. The system also includes first circuitry to receive input signals and to produce output signals, and wherein the first circuitry speculates that the cosmic ray detector will not detect cosmic rays, but in response to the cosmic ray detection signals, the first circuitry re-performs at least some operations. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，系统包括用于检测宇宙射线并产生指示检测到的宇宙射线的宇宙射线检测信号的宇宙射线检测器。 该系统还包括用于接收输入信号并产生输出信号的第一电路，并且其中第一电路推测宇宙射线检测器不会检测宇宙射线，但是响应于宇宙射线检测信号，第一电路在 最少一些操作。 描述和要求保护其他实施例。

公开(公告)号：WO1997035247A1

公开(公告)日：1997-09-25

申请号：PCT/US1997004028

申请日：1997-03-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HANNAH, Eric, C.

IPC: G06F03/04

CPC classification number: H04N1/00238 ,  H04N1/00236 ,  H04N1/00241

Abstract: A copier (10) for rendering an image of an object onto a physical medium includes a scanner (60), a printer (80) and an external processor (30). The scanner (60) and the printer (80) are coupled to the external processor (30) by a high-speed serial bus (61) having a latency and a maximum signal transmission rate sufficient to enable transmission to the external processor (30) of the digital image signal generated by the scanner (60) which represent the image of the object without prior interim storage of the digital image signals in a buffer on board the scanner (60). The high-speed serial bus (61) further has a latency and a maximum signal transmission rate sufficient to enable transmission of the digital image signals from the external processor (30) to the printer (80) for rendering the digital image signals in a buffer on board the printer (80). In an embodiment, the external processor (30) is capable of processing the digital image signals and the scanner (60) is capable of transmitting the digital image signals without prior on-board digital processing of the digital image signals in the scanner (60) and the printer (80) is capable of rendering the digital image signals without prior on-board digital processing of the digital image signals in the printer (80).

Abstract translation: 用于将物体的图像呈现到物理介质上的复印机（10）包括扫描器（60），打印机（80）和外部处理器（30）。 扫描器（60）和打印机（80）通过高速串行总线（61）耦合到外部处理器（30），该高速串行总线具有足以使能够传送到外部处理器（30）的等待时间和最大信号传输速率， 由扫描器（60）生成的数字图像信号（其代表对象的图像）而没有将数字图像信号预先临时存储在扫描器（60）上的缓冲器中。 高速串行总线（61）还具有足以使数字图像信号从外部处理器（30）传输到打印机（80）的延迟和最大信号传输速率，以将数字图像信号呈现在缓冲器 在打印机（80）上。 在一个实施例中，外部处理器（30）能够处理数字图像信号，并且扫描器（60）能够传输数字图像信号而无需先前对扫描器（60）中的数字图像信号进行数字处理， 并且打印机（80）能够呈现数字图像信号，而无需对打印机（80）中的数字图像信号进行预先的板载数字处理。

公开(公告)号：WO1997033228A1

公开(公告)日：1997-09-12

申请号：PCT/US1997003630

申请日：1997-03-10

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HANNAH, Eric, C.

IPC: G06F13/00

CPC classification number: G06F21/71 ,  G06F21/82 ,  G06F21/85 ,  G06K15/02 ,  G06K2215/0005 ,  G06K2215/0011

Abstract: This invention is a printer (30) which contains a print engine (31) for printing an image onto a physical medium. The print engine (31) receives signals representing the image to be printed directly from an external computer (20). The printer (30) is coupled to the external computer (20) by a high speed serial bus (26) that enables the printer (30) to print the images without prior interim storage of the signals in an onboard buffer in the printer (30). The signals may be processed in the external computer (20) before being transmitted to the printer (30), thereby eliminating the need for a processor onboard the printer (30).

Abstract translation: 本发明是一种包含用于将图像打印到物理介质上的打印引擎（31）的打印机（30）。 打印引擎（31）从外部计算机（20）直接接收表示要打印的图像的信号。 打印机（30）通过高速串行总线（26）耦合到外部计算机（20），该高速串行总线（26）使得打印机（30）能够打印图像，而无需在打印机（30）内的板载缓冲器中暂时存储信号 ）。 信号可以在被传送到打印机（30）之前在外部计算机（20）中被处理，从而消除对打印机（30）上的处理器的需要。

公开(公告)号：WO1997037305A1

公开(公告)日：1997-10-09

申请号：PCT/US1997004905

申请日：1997-03-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  TRAW, C., Brendan, S. ,  HANNAH, Eric, C. ,  HAUCK, Jerrold, V. ,  COULSON, Richard, L. ,  HOSLER, Brad, W.

IPC: G06F11/00

CPC classification number: G06F21/85 ,  G06F21/42 ,  G06F21/55 ,  G06F2211/002 ,  G06F2221/2103 ,  G06F2221/2129

Abstract: Security from an unwanted intrusion into a computer system (12) is provided by coupling a host component (10) with a peripheral component (16-18) using a high-speed serial bus (14.1-14.4) having a high-speed physical layer and using features of the bus (14.1-14.4) to implement the security. In an embodiment, the high-speed serial bus (14.1-14.4) has a secondary bus layer that is used to implement a number of the security features of the invention.

Abstract translation: 通过使用具有高速物理层（14.1-14.4）的高速串行总线（14.1-14.4）将主机组件（10）与外围组件（16-18）耦合，从而防止来自计算机系统（12）的不想要的入侵的安全性 并使用总线（14.1-14.4）的功能实现安全。 在一个实施例中，高速串行总线（14.1-14.4）具有辅助总线层，其用于实现本发明的许多安全特征。

公开(公告)号：WO1997037309A1

公开(公告)日：1997-10-09

申请号：PCT/US1997004995

申请日：1997-03-27

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  HANNAH, Eric, C. ,  COULSON, Richard, L. ,  HAUCK, Jerrold, V.

IPC: G06F13/00

CPC classification number: G06F3/0601 ,  G06F13/4286 ,  G06F2003/0692

Abstract: A mass storage device (30) having a storage medium (31) on which digital signals can be stored. The mass storage device (30) is coupleable to a computer (20) through a high-speed serial bus (25). The high-speed serial bus has a latency and a signal transmission rate sufficient to enable transmission of digital signals between the mass storage device and the computer without interim storage (12 and 13) of the digital signals in a buffer (13) inside the mass storage device (10). The computer has a processor (22) capable of processing the digital signals and the digital signals may be transmitted between the mass storage device and the computer without processing of the digital signals by a processor (13) in the mass storage device.

Abstract translation: 一种具有可存储数字信号的存储介质（31）的海量存储装置（30）。 大容量存储装置（30）通过高速串行总线（25）可耦合到计算机（20）。 高速串行总线具有足够的延迟和信号传输速率，以便能够在大容量存储设备和计算机之间传输数字信号，而无需在质量块内的缓冲器（13）中的数字信号的中间存储（12和13） 存储装置（10）。 计算机具有能够处理数字信号的处理器（22），并且可以在大容量存储设备和计算机之间传输数字信号，而不用大容量存储设备中的处理器（13）处理数字信号。