公开(公告)号：WO0139254A2

公开(公告)日：2001-05-31

申请号：PCT/US0042211

申请日：2000-11-15

Applicant: MENTOR GRAPHICS CORP

Inventor： RAJSKI JANUSZ ,  TYSZER JERZY ,  KASSAB MARK ,  MUKHERJEE NILANJAN

IPC: G01R31/28 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3185 ,  H01L

CPC classification number: G01R31/318335 ,  G01R31/31813 ,  G01R31/318547

Abstract: A method for applying test patterns to scan chains (26) in a circuit-under-test (24). The method includes providing a compressed test pattern (32) of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor (36)such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

Abstract translation: 一种用于将测试图案应用于被测电路（24）中的扫描链（26）的方法。 该方法包括提供压缩的测试图案（32）; 当压缩的测试图案被提供时，将压缩的测试图案解压缩成解压缩的测试图案; 并将解压后的测试图案应用于被测电路的扫描链。 取决于将要生成解压缩比特的方式，提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作以相同或不同的时钟速率同步执行。 执行解压缩的电路包括解压缩器（36），例如线性有限状态机，适用于接收压缩的位测试模式。 随着压缩测试码型的接收，解压缩器将测试码型解压缩成解压缩的测试码型。 该电路进一步包括用于测试电路逻辑的扫描链，扫描链耦合到解压缩器并适于接收解压缩的测试模式。

公开(公告)号：WO2007098167A3

公开(公告)日：2008-04-24

申请号：PCT/US2007004422

申请日：2007-02-19

Applicant: MENTOR GRAPHICS CORP ,  MRUGALSKI GRZEGORZ ,  RAJSKI JANUSZ ,  TYSZER JERZY ,  CHENG WU-TUNG ,  MUKHERJEE NILANJAN ,  KASSAB MARK

Inventor： MRUGALSKI GRZEGORZ ,  RAJSKI JANUSZ ,  TYSZER JERZY ,  CHENG WU-TUNG ,  MUKHERJEE NILANJAN ,  KASSAB MARK

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

Abstract: Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 100Ox. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract translation: 这里公开了所谓的“X-press”测试响应压实机的示例性实施例。 所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。 所公开技术的某些实施方案提供大约1000x的压实比。 所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。 扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。 本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

公开(公告)号：WO2009039316A3

公开(公告)日：2009-08-20

申请号：PCT/US2008076911

申请日：2008-09-18

Applicant: MENTOR GRAPHICS CORP ,  MUKHERJEE NILANJAN ,  POGIEL ARTUR ,  RAJSKI JANUSZ ,  TYSZER JERZY

Inventor： MUKHERJEE NILANJAN ,  POGIEL ARTUR ,  RAJSKI JANUSZ ,  TYSZER JERZY

IPC: G11C29/56 ,  G11C29/40

CPC classification number: G11C29/56 ,  G11C29/40 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/1208

Abstract: Disclosed are methods and devices for temporally compacting test response signatures of failed memory tests in a memory built-in self -test environment, to provide the ability to carry on memory built-in self-test operations even with the detection of multiple time related memory test failures. In some implementations of the invention, the compacted test response signatures are provided to an automated test equipment device along with memory location information. According to various implementations of the invention, an integrated circuit with embedded memory (204) and a memory BIST controller (206) also includes a linear feedback structure (410) for use as a signature register that can temporally compact test response signatures from the embedded memory array during a test step of a memory test. In various implementations the integrated circuit may also include a failing words counter (211), a failing column indicator (213), and/or a failing row indicator (214) to collect memory location information for a failing test response.

Abstract translation: 公开了用于在存储器内置自测环境中暂时压缩失败存储器测试的测试响应特征的方法和设备，以提供即使在检测到多个时间相关存储器的情况下进行存储器内置自检操作的能力 测试失败。 在本发明的一些实施方案中，将压实的测试响应签名与存储器位置信息一起提供给自动测试设备设备。 根据本发明的各种实施方式，具有嵌入式存储器（204）和存储器BIST控制器（206）的集成电路还包括用作签名寄存器的线性反馈结构（410），其可以临时压缩来自嵌入式 在内存测试的测试步骤中的内存阵列。 在各种实现中，集成电路还可以包括故障字计数器（211），故障列指示器（213）和/或故障行指示器（214），以收集故障测试响应的存储器位置信息。

公开(公告)号：WO2006138488A2

公开(公告)日：2006-12-28

申请号：PCT/US2006023360

申请日：2006-06-14

Applicant: MENTOR GRAPHICS CORP ,  MUKHERJEE NILANJAN ,  JAHANGIRI JAY ,  PRESS RONALD ,  CHENG WU-TUNG

Inventor： MUKHERJEE NILANJAN ,  JAHANGIRI JAY ,  PRESS RONALD ,  CHENG WU-TUNG

IPC: G01R31/28 ,  G06F11/00

CPC classification number: G01R31/318541 ,  G01R31/318572 ,  G01R31/318583

Abstract: Methods, apparatus, and systems for testing integrated circuits using one or more boundary scan cells are disclosed. The methods, apparatus, and systems can be used, for example, to apply at-speed test patterns through one or more boundary scan cells. For instance, in one exemplary non limiting embodiment, a circuit is disclosed comprising one or more boundary scan cells coupled to primary input ports or primary output ports of a circuit-under-test. The circuit further includes a boundary scan cell controller configured to apply test control signals to the one or more boundary scan cells. In this embodiment, the controller is configured to operate in a mode of operation whereby the controller applies test control signals to the one or more boundary scan cells that correspond to test control signals used to control one or more internal scan chains of the circuit-under-test during testing. The control signals of this exemplary embodiment include an at-speed-clock signal generated outside of the boundary scan cell controller.

Abstract translation: 公开了使用一个或多个边界扫描单元测试集成电路的方法，装置和系统。 方法，装置和系统可以用于例如通过一个或多个边界扫描单元应用速度测试图案。 例如，在一个示例性非限制性实施例中，公开了一种电路，其包括耦合到被测电路的主输入端口或主输出端口的一个或多个边界扫描单元。 电路还包括配置成将测试控制信号施加到一个或多个边界扫描单元的边界扫描单元控制器。 在该实施例中，控制器被配置为在操作模式下操作，由此控制器将测试控制信号施加到对应于用于控制电路的一个或多个内部扫描链的测试控制信号的一个或多个边界扫描单元 测试中测试。 该示例性实施例的控制信号包括在边界扫描单元控制器之外产生的一个速度 - 时钟信号。

公开(公告)号：WO2006055862A3

公开(公告)日：2006-09-14

申请号：PCT/US2005042029

申请日：2005-11-18

Applicant: MENTOR GRAPHICS CORP ,  MUKHERJEE NILANJAN ,  DU XIAOGANG ,  CHENG WU-TUNG

Inventor： MUKHERJEE NILANJAN ,  DU XIAOGANG ,  CHENG WU-TUNG

IPC: G11C29/00 ,  G01R27/28 ,  G01R31/28 ,  G06F11/00

CPC classification number: G01R31/3187 ,  G01R31/31724 ,  G01R31/318519 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/20 ,  G11C2029/0401 ,  G11C2029/0405 ,  G11C2029/3602 ,  G11C2029/5604

Abstract: Programmable memory built-in-self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing.

Abstract translation: 公开了可编程存储器内置自检（MBIST）方法，装置和系统。 所公开的技术的示例性实施例可以用于例如在制造测试期间测试位于集成电路上的一个或多个存储器。