公开(公告)号：WO2022197345A1

公开(公告)日：2022-09-22

申请号：PCT/US2022/011011

申请日：2022-01-03

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： YUENYONGSGOOL, Yong ,  BOWLING, Stephen ,  OVALLE, Pedro

IPC: H03K17/16 ,  H03K5/04

Abstract: An apparatus includes an adjustment circuit configured to receive a pulsed-width modulation (PWM) input, generate an adjusted PWM signal based upon the PWM input, and determine that a first pulse of the PWM input is shorter than a runt signal limit. The adjustment circuit is configured to, in the adjusted PWM signal, extend the first pulse of the PWM input based on the determination that the PWM input is shorter than the runt signal limit, and output the adjusted PWM signal to an electronic device.

公开(公告)号：WO2019084224A1

公开(公告)日：2019-05-02

申请号：PCT/US2018/057437

申请日：2018-10-25

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： YUENYONGSGOOL, Yong ,  BOWLING, Stephen ,  VAN EEDEN, Cobus ,  WOJEWODA, Igor ,  RAJ, Naveen

IPC: G06F13/28

Abstract: A memory management circuit includes a direct memory access (DMA) channel. The DMA channel incudes logic configured to receive a buffer of data to be written using DMA. The DMA channel further includes logic to perform bit manipulation in real-time during a DMA write cycle of the first buffer of data.

公开(公告)号：WO2019079083A3

公开(公告)日：2019-04-25

申请号：PCT/US2018/055151

申请日：2018-10-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BOWLING, Stephen ,  YUENYONGSGOOL, Yong ,  WOJEWODA, Igor ,  PHOENIX, Timothy ,  FERNANDES, Dereck ,  BRADLEY, Steve ,  BALU, Manivannan

IPC: G11C29/12 ,  G11C29/14 ,  G06F15/80 ,  G11C29/48 ,  G11C29/26

Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

公开(公告)号：WO2019089872A1

公开(公告)日：2019-05-09

申请号：PCT/US2018/058615

申请日：2018-11-01

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BARTLING, James E. ,  BOWLING, Stephen

IPC: H03M1/10 ,  H03M1/12

Abstract: A constant current source, a stable time base and a capacitor are used to self-check operation of an analog-to-digital convertor (ADC) by charging the capacitor for a pre-determined amount of time to produce a voltage thereon. This voltage will be proportional to the amount of time that the capacitor was charged. Multiple points on the ADC transfer function can be verified in this self-check procedure simply by varying the amount of time for charging of the capacitor. Relative accuracy among test points may then be easily obtained. Absolute accuracy may be obtained by using an accurate clock reference for the time base, a known current source and capacitor value.

公开(公告)号：WO2013116451A2

公开(公告)日：2013-08-08

申请号：PCT/US2013/024032

申请日：2013-01-31

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BOWLING, Stephen ,  BARTLING, James, E.

IPC: G06F1/04

CPC classification number: G06F1/06 ,  G06F1/04 ,  G06F1/14

Abstract: A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.

Abstract translation: 微控制器具有可编程时基，其中所述时基具有触发输入以启动所述时基的定时器或计数器，并且其中所述时基可被配置为在以第一模式接收到触发信号时操作以产生多个定时器/计数器事件 直到控制寄存器中的复位位被置位，并且在第二模式中产生单个定时器/计数器事件信号，并且其中时基可被配置为在第三模式下操作以产生预定数量的定时器/计数器事件信号， 其中预定数量由寄存器的多个位来定义。

公开(公告)号：WO2009137573A1

公开(公告)日：2009-11-12

申请号：PCT/US2009/042974

申请日：2009-05-06

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  KRIS, Bryan ,  BOWLING, Stephen

Inventor： KRIS, Bryan ,  BOWLING, Stephen

IPC: H03K7/00 ,  H02M1/00

CPC classification number: H03K7/08 ,  H02M1/38 ,  H03K5/1515

Abstract: Dead time compensated complementary pulse width modulation (PWM) signals (PWMH, PWML) are derived from a PWM generator by first applying time period compensation to the PWM generator signal (450) based upon the direction of current flow in an inductive load (correction control: 440) being controlled by the PWM generator. Dead time is then applied to the compensated PWM generator signal (462) for producing complementary dead time compensated PWM signals (PWMH, PWML) for controlling power switching circuits driving the inductive load.

Abstract translation: 基于电感负载中的电流方向（校正控制），首先对PWM发生器信号（450）施加时间周期补偿，从PWM发生器导出死区补偿互补脉宽调制（PWMH）信号（PWMH，PWML） ：440）由PWM发生器控制。 然后将死时间施加到补偿的PWM发生器信号（462），用于产生用于控制驱动感性负载的功率开关电路的互补死区时间补偿PWM信号（PWMH，PWML）。

公开(公告)号：WO2016145284A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/021945

申请日：2016-03-11

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： KRIS, Bryan ,  BOWLING, Stephen ,  DUMAIS, Alex

IPC: H02M1/08 ,  H02M3/155 ,  H02M3/335

CPC classification number: H03K7/08 ,  H02M1/08 ,  H02M3/157 ,  H02M2001/0012

Abstract: A number of standard PWM generators produce PWM signals that may be used to drive the power stages for Full-Bridge, Feed-Forward, Push-Pull, Phase-Shift Zero Voltage Transition (ZVT), and other switched mode power supply (SMPS) conversion topologies. These PWM signals may be fed to logic functions of a combinatorial logic block. Appropriate PWM signals are selected as operands along with desired logic function(s) that operates on these input operands. The resultant combinatorial PWM signals may then be used directly or may be fed through dead-time processing circuitry prior to outputting to an application circuit. In addition to the combinatorial logic functions, sequential logic functions may also be used to provide sequential PWM signals, e.g., synchronous sequential, asynchronous sequential, and/or sequential-combinatorial PWM signals.

Abstract translation: 许多标准PWM发生器产生可用于驱动全桥，前馈，推挽，相移零电压转换（ZVT）和其他开关模式电源（SMPS）的功率级的PWM信号， 转换拓扑。 这些PWM信号可以被馈送到组合逻辑块的逻辑功能。 选择适当的PWM信号作为操作数以及对这些输入操作数进行操作的所需逻辑功能。 然后可以直接使用所得到的组合PWM信号，或者可以在输出到应用电路之前通过死区时间处理电路馈送。 除了组合逻辑功能之外，顺序逻辑功能还可用于提供顺序PWM信号，例如同步顺序，异步顺序和/或顺序组合PWM信号。

公开(公告)号：WO2013048726A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/054733

申请日：2012-09-12

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  BOWLING, Stephen ,  WOJEWODA, Igor

Inventor： BOWLING, Stephen ,  WOJEWODA, Igor

IPC: G06F1/14 ,  G06F1/32

CPC classification number: G06F1/14 ,  G06F1/3243 ,  G06F1/3287 ,  G06F15/7814 ,  G06F15/7853 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: - a timer being clocked by an independent clock signal; - a comparator coupled with a timer register of said timer and having an output generating an output signal; - an event register coupled with said comparator; - a delta time register; and - an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Abstract translation: 微控制器具有中央处理单元（CPU），多个外围设备和可编程调度器单元，其具有： - 由独立时钟信号计时的定时器; - 与所述定时器的定时器寄存器耦合并具有产生输出信号的输出的比较器; - 与所述比较器耦合的事件寄存器; - 增量时间寄存器 以及 - 由比较器的输出信号和第一和第二输入和输出控制的算术逻辑单元，其中第一输入与定时器寄存器或事件寄存器耦合，第二输入与增量时间寄存器耦合， 输出与事件寄存器耦合。

公开(公告)号：WO2008030751A2

公开(公告)日：2008-03-13

申请号：PCT/US2007/077200

申请日：2007-08-30

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  GULSEN, John, K. ,  BOWLING, Stephen

Inventor： GULSEN, John, K. ,  BOWLING, Stephen

IPC: H05B41/392

CPC classification number: H05B41/3921

Abstract: Pulse Density Modulation (PDM) is used to control the amount of light from a fluorescent lamp by applying a voltage to the lamp filaments at a low frequency that is approximately at a series resonant frequency of the lamp ballast inductor and the lamp filament capacitor, no voltage and a voltage at a high frequency. The lamp gas ionizes to produce light only when the low frequency voltage is applied. The fluorescent lamp gas does not ionize when the voltage at the high frequency is applied, but the high frequency voltage keeps the lamp filaments warm during low light output conditions. The low frequency, no and high frequency voltages have time periods that occur within a modulation frame time period that repeats continuously. The ratio of the low frequency voltage time period, and the no voltage and/or high frequency voltage time periods determine the light output of the fluorescent lamp.

Abstract translation: 脉冲密度调制（PDM）用于通过以大致为灯镇流电感器和灯丝电容器的串联谐振频率的低频施加电压至灯丝来控制来自荧光灯的光量，否则 电压和高频电压。 仅当施加低频电压时，灯气体才会电离以产生光。 当施加高频时，荧光灯气体不会电离，而在低光输出条件下，高频电压使灯丝保持温暖。 低频，无和高频电压具有发生在连续重复的调制帧时间周期内的时间周期。 低频电压时间段和无电压和/或高频电压时间周期的比率决定了荧光灯的光输出。

公开(公告)号：WO2022132575A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/062758

申请日：2021-12-10

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： BOWLING, Stephen ,  BALU, Manivannan ,  PHOENIX, Timothy ,  RANGARAJAN, Sankar

IPC: G06F11/36

Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.