公开(公告)号：WO2012127177A1

公开(公告)日：2012-09-27

申请号：PCT/GB2011/050543

申请日：2011-03-18

Applicant: PANASONIC CORPORATION ,  STANSFIELD, Anthony

Inventor： STANSFIELD, Anthony

IPC: G11C29/12 ,  G11C29/48 ,  G11C8/16 ,  H03K19/177

CPC classification number: G11C29/12 ,  G11C8/16 ,  G11C11/41 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/0401 ,  H03K19/1776

Abstract: A configuration memory for a programmable logic device (PLD) is described comprising a plurality of memory cells for a configuration memory of a programmable logic device (PLD) each memory cell comprising a storage element and first input means and second input means each being independently operable to provide access to the storage element. The second input means of at least one of the plurality of memory cells is arranged to receive control signals from a test interface for providing test signals to the PLD.

Abstract translation: 描述了可编程逻辑器件（PLD）的配置存储器，其包括用于可编程逻辑器件（PLD）的配置存储器的多个存储器单元，每个存储器单元包括存储元件和第一输入装置，以及第二输入装置，每个存储器单元可独立操作 以提供对存储元件的访问。 多个存储器单元中的至少一个的第二输入装置被布置成从测试接口接收控制信号，以向PLD提供测试信号。

公开(公告)号：WO2005043276A3

公开(公告)日：2006-06-01

申请号：PCT/IL2004000941

申请日：2004-10-13

Applicant: MILSYS LTD ,  AVRAHAM MEIR

Inventor： AVRAHAM MEIR

IPC: G08C25/02 ,  G01R31/3185 ,  G06F20060101 ,  G11C29/00 ,  G11C29/48 ,  H04L1/18

CPC classification number: G11C29/48 ,  G01R31/318513 ,  G11C29/1201 ,  G11C2029/0401 ,  G11C2029/1208

Abstract: A method of testing a SIP that has a CPU, a nonvolatile memory and a volatile memory. First, the CPU is used to test the memories. Then the CPU is tested separately. Preferably, the programs for testing the memories are pre-stored in and loaded from the nonvolatile memory into the volatile memory and are executed by the CPU in the volatile memory. Preferably, the test results are stored in the nonvolatile memory.

Abstract translation: 一种测试具有CPU，非易失性存储器和易失性存储器的SIP的方法。 首先，CPU用于测试记忆。 然后分别测试CPU。 优选地，用于测试存储器的程序预先存储在非易失性存储器中并从非易失性存储器加载到易失性存储器中，并且由易失性存储器中的CPU执行。 优选地，将测试结果存储在非易失性存储器中。

公开(公告)号：WO2005017959A3

公开(公告)日：2005-09-09

申请号：PCT/US2004022509

申请日：2004-07-15

Applicant: FREESCALE SEMICONDUCTOR INC ,  TRAN TU-ANH ,  EGUCHI RICHARD K ,  HARPER PETER R ,  LEE CHU-CHUNG ,  WILLIAMS WILLIAM M ,  YONG LOIS

Inventor： TRAN TU-ANH ,  EGUCHI RICHARD K ,  HARPER PETER R ,  LEE CHU-CHUNG ,  WILLIAMS WILLIAM M ,  YONG LOIS

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3187 ,  G11C29/48 ,  G01R31/02

CPC classification number: G11C29/1201 ,  G01R31/2884 ,  G01R31/31715 ,  G01R31/3187 ,  G11C29/48 ,  H01L2224/05554

Abstract: A semiconductor device (10) has a large number of bond pads (24) on the periphery for wirebonding. The semiconductor device (10) has a module (12) as well as other circuitry, but the module (12) takes significantly longer to test than the other circuitry. A relatively small number of the bond pads (20), the module bond pads (20), are required for the module testing due, at least in part, to the semiconductor device having a built-in self-test (BIST) (16) circuitry. The functionality of these module bond pads (22) is duplicated on the top surface of and in the interior of the semiconductor device (10) with module test pads (22) that are significantly larger than the bond pads (24) on the periphery. Having large pads (22) for testing allows longer probe needles, thus increasing parallel testing capability. Duplicating the functionality is achieved through a test pad interface so that the module bond pads (20) and the module test pads (22) do not have to be shorted together.

Abstract translation: 半导体器件（10）在外围具有大量的接合焊盘（24）用于引线接合。 半导体器件（10）具有模块（12）以及其它电路，但是模块（12）需要比其他电路更长的测试时间。 由于至少部分地由具有内置自检（BIST）的半导体器件（BIST）（16），模块测试所需的相对较少数量的接合焊盘（20），模块接合焊盘（20） ）电路。 这些模块接合焊盘（22）的功能性被复制在半导体器件（10）的内表面上和在半导体器件（10）的内部，其中模块测试焊盘（22）明显大于外围的接合焊盘（24）。 具有大的用于测试的焊盘（22）允许更长的探针，因此增加了并行测试能力。 通过测试垫接口实现复制功能，使得模块接合焊盘（20）和模块测试焊盘（22）不必一起短路。

公开(公告)号：WO2004072660A3

公开(公告)日：2005-04-28

申请号：PCT/US2004004271

申请日：2004-02-13

Applicant: MENTOR GRAPHICS CORP ,  RAJSKI JANUSZ ,  TYSZER JERZY ,  WANG CHEN ,  MRUGALSKI GRZEGORZ ,  POGIEL ARTUR

Inventor： RAJSKI JANUSZ ,  TYSZER JERZY ,  WANG CHEN ,  MRUGALSKI GRZEGORZ ,  POGIEL ARTUR

IPC: G01R31/3185 ,  G01R31/319 ,  G11C29/40 ,  G11C29/48 ,  G06F11/00 ,  G01R31/28

CPC classification number: G01R31/318566 ,  G01R31/31703 ,  G01R31/318536 ,  G01R31/318583 ,  G01R31/31921 ,  G11C29/40 ,  G11C29/48 ,  G11C2029/3202

Abstract: The present disclosure describes embodiments of a compactor (706) for compressing test results in an integrated circuit (704) and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation ("EDA") software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

Abstract translation: 本公开描述了用于压缩集成电路（704）中的测试结果的压实器（706）的实施例以及用于使用和设计这些实施例的方法。 所公开的压实机可以例如用作任何基于扫描的设计的一部分。 此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。 还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

公开(公告)号：WO0229824A3

公开(公告)日：2003-05-01

申请号：PCT/CA0101365

申请日：2001-09-26

Applicant: CONCORD IDEA CORP ,  LAI BOSCO

Inventor： LAI BOSCO

IPC: G01R31/3183 ,  G01R31/28 ,  G11C29/48 ,  G01R31/319 ,  G01R31/3193 ,  G06F11/277 ,  G11C29/00

CPC classification number: G11C29/48

Abstract: The invention disclosed herein is a system and method for testing integrated circuit devices, including memory chips. The devices under test are subject to behavioural testing, in which a copy of signals in an application system is directed to the device under test, or to an electronic component connected to the device under test. This permits the device under test to be tested under the operating conditions of the application system, which is preferably similar to the actual application environment in which the device under test will ultimately be used. Conventional tests, including pattern testing and/or parametric tests, may also be performed on devices under test, if desired.

Abstract translation: 本文公开的发明是用于测试包括存储器芯片的集成电路器件的系统和方法。 被测设备将进行行为测试，其中应用系统中的信号副本被引导到被测设备，或连接到被测设备的电子部件。 这允许在应用系统的操作条件下测试被测设备，其优选地类似于将最终使用被测设备的实际应用环境。 如果需要，常规测试，包括模式测试和/或参数测试也可以在被测设备上进行。

公开(公告)号：WO2018136124A1

公开(公告)日：2018-07-26

申请号：PCT/US2017/058087

申请日：2017-10-24

Applicant: GOOGLE LLC

Inventor： SHIU, Shinye

IPC: G11C5/04 ,  G11C5/06 ,  G11C5/14 ,  G11C29/48 ,  H01L25/065 ,  G11C7/10 ,  G11C11/4093

Abstract: This document describes apparatuses and techniques for integrated DRAM with low-voltage swing I/O. In some aspects, a dynamic random access memory (DRAM) die and application processor (AP) die are mounted to a system-in-package (SiP) die carrier that includes one or more redistribution layers. The DRAM die and AP die are located adjacent to each other on the die-carrier such that respective memory inputs/outputs of each die are proximate the other inputs/outputs.

公开(公告)号：WO2018026946A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/045143

申请日：2017-08-02

Applicant: CELERINT, LLC

Inventor： ROBERTS, JR., Howard H.

IPC: G01R1/04 ,  G01R31/26 ,  G01R31/28 ,  G01R31/319 ,  G01R31/3193 ,  G11C29/48

Abstract: A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.

Abstract translation: 提供了一种用于对在多个不同温度下分成第一子组和第二子组的半导体组进行连续单插入半导体测试的方法。 单次插入半导体测试通过顺序地执行测试循环来执行，其特征在于，测试器交替执行第一子组的温度测试时段和温度斜坡时段，同时执行第二子组的温度斜坡时段和温度测试时段。 温度测试周期在两个或更多不同的温度下运行。 当测试时间等于或大于斜坡时间时，单次插入测试序列完全消除了测试仪索引时间，并且当测试时间小于斜坡时间时，大大减少了测试仪索引时间。

公开(公告)号：WO2004001568A3

公开(公告)日：2004-03-18

申请号：PCT/IB0302380

申请日：2003-06-19

Applicant: MELEXIS NV ,  DE WINTER RUDI

Inventor： DE WINTER RUDI

IPC: G01R31/317 ,  G01R31/3185 ,  G11C7/10 ,  G11C29/48 ,  H03K19/173

CPC classification number: G11C29/1201 ,  G01R31/31701 ,  G01R31/318572 ,  G11C7/1078 ,  G11C7/109 ,  G11C29/48 ,  H03K19/1732

Abstract: An integrated circuit (102) comprises one or more integrated circuit elements which may interact with other circuitry via one or more input/output pins. In the present invention the circuit elements include and interface element (101) for interfacing with external test circuitry. The interface element communicates with the external test circuitry via a single input/output pin (201) dedicated for testing.

Abstract translation: 集成电路（102）包括一个或多个集成电路元件，其可以经由一个或多个输入/输出引脚与其它电路相互作用。 在本发明中，电路元件包括用于与外部测试电路接口的接口元件（101）。 接口元件通过专用于测试的单个输入/输出引脚（201）与外部测试电路通信。

公开(公告)号：WO0195117A3

公开(公告)日：2002-08-08

申请号：PCT/RU0100234

申请日：2001-06-06

Applicant: ABROSIMOV IGOR ANATOLIEVICH ,  KLOTCHKOV ILYA VALERIEVICH

Inventor： ABROSIMOV IGOR ANATOLIEVICH ,  KLOTCHKOV ILYA VALERIEVICH

IPC: G11C29/48 ,  G11C29/56 ,  G11C29/00

CPC classification number: G11C29/56012 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602

Abstract: The present invention relates generally to data processing systems, in particular, to computer-controlled automatic test systems for testing integrated circuits, and more particularly to memory test systems which interface with high speed protocol memories such as synchronous DRAM, in particular DDR.A data processing system comprises a data transmitter having a plurality of data transmitting sections operable in parallel for transmitting data, wherein the data trasmitter additionally comprises a circuit for synchronising said parallel data transmitting sections; a programmable frequency clock generator for generating a clock signal, wherein said programmed frequency includes a full-frequency and a low-frequency, the low frequency being a quotient of the full frequency and a number of said data transmitting sections; a multiplexer that receives data from said data transmitting sections at said low frequency and provides multiplexed output data at said full frequency; a plurality of registers for latching data and supplying latched data to a plurality of logic devices; wherein said data transmitting sections, said registers and said receiving devices operate at said low frequency; while said output data are transmitted and received at said full frequency.

Abstract translation: 本发明一般涉及数据处理系统，特别涉及用于测试集成电路的计算机控制的自动测试系统，更具体地涉及与诸如同步DRAM（特别是DDR）的高速协议存储器接口的存储器测试系统.A数据 处理系统包括数据发送器，具有可并行操作以发送数据的多个数据发送部分，其中所述数据传送器还包括用于同步所述并行数据发送部分的电路; 用于产生时钟信号的可编程频率时钟发生器，其中所述编程频率包括全频率和低频率，所述低频率是所述全频率的商和所述数据发送部分的数量; 多路复用器，以所述低频率从所述数据发送部分接收数据，并以所述全频率提供复用的输出数据; 多个寄存器，用于锁存数据并将锁存数据提供给多个逻辑器件; 其中所述数据发送部分，所述寄存器和所述接收装置以所述低频工作; 而所述输出数据以所述全频率发送和接收。

公开(公告)号：WO01050474A1

公开(公告)日：2001-07-12

申请号：PCT/US2000/015476

申请日：2000-06-05

IPC: G01R31/28 ,  G06F11/22 ,  G06F12/16 ,  G11C29/48 ,  G11C29/56 ,  G11C29/00 ,  H04L12/26

CPC classification number: G06F11/2289 ,  G11C29/48

Abstract: A method and arrangement for testing external memories of different types coupled to a network interface controller interprets the results of the memory test differently in accordance with the memory test differently in accordance with the memory type. A fail state indicator is used by test controller to indicate the proper offset to add or subtract to a test address to calculate the actual failing memory location.

Abstract translation: 用于测试耦合到网络接口控制器的不同类型的外部存储器的方法和装置根据存储器类型不同地根据存储器测试不同地解释存储器测试的结果。 测试控制器使用故障状态指示器来指示适当的偏移量，以对测试地址进行加法或减法，以计算实际的故障存储器位置。