公开(公告)号：WO2017106523A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/066967

申请日：2016-12-15

Applicant: MICROSEMI SOC CORPORATION

Inventor： MCCOLLUM, John, L. ,  HAMDY, Esmat, Z.

IPC: G11C13/00 ,  H01L27/24

CPC classification number: H03K19/1776 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/12

Abstract: A low-leakage resistive random access memory cell includes a complementary pair of bit lines and a switch node. A first ReRAM device is connected to a first one of the bit lines. A p-channel transistor has a source connected to the ReRAM device, a drain connected to the switch node, and a gate connected to a bias potential. A second ReRAM device is connected to a second one of the bit lines. An n-channel transistor has a source connected to the ReRAM device a drain connected to the switch node, and a gate connected to a bias potential.

Abstract translation: 低泄漏电阻随机存取存储器单元包括互补位线对和开关节点。 第一ReRAM器件连接到第一位线。 P沟道晶体管具有连接到ReRAM器件的源极，连接到开关节点的漏极以及连接到偏置电势的栅极。 第二ReRAM器件连接到第二条位线。 n沟道晶体管具有连接到ReRAM器件的源极，连接到开关节点的漏极以及连接到偏置电势的栅极。