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    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES
    2.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR GATING CONFIGURATIONS AND IMPROVED CONTACTS IN NANOWIRE-BASED ELECTRONIC DEVICES 审中-公开
    用于在纳米级电子设备中进行配置和改进联系的方法，系统和设备

    公开(公告)号：WO2007030126A2

    公开(公告)日：2007-03-15

    申请号：PCT/US2005/037237

    申请日：2005-10-14

    Applicant: NANOSYS, INC. ,  MOSTARSHED, Shahriar ,  CHEN, Jian ,  LEON, Francisco ,  PAN, Yaoling ,  ROMANO, Linda T.

    Inventor： MOSTARSHED, Shahriar ,  CHEN, Jian ,  LEON, Francisco ,  PAN, Yaoling ,  ROMANO, Linda T.

    IPC: H01L29/76

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78681 ,  H01L29/7869 ,  Y10S977/762 ,  Y10S977/932 ,  Y10S977/938

    Abstract: Methods, systems, and apparatuses for electronic devices having improved gate structures are described. An electronic device includes at least one nanowire. A gate contact is positioned along at least a portion of a length of the at least one nanowire. A dielectric material layer is between the gate contact and the at least one nanowire. A source contact and a drain contact are in contact with the at least one nanowire. At least a portion of the source contact and/or the drain contact overlaps with the gate contact along the nanowire the length. In another aspect, an electronic device includes a nanowire having a semiconductor core surrounded by an insulating shell layer. A ring shaped first gate region surrounds the nanowire along a portion of the length of the nanowire. A second gate region is positioned along the length of the nanowire between the nanowire and the substrate. A source contact and a drain contact are coupled to the semiconductor core of the nanowire at respective exposed portions of the semiconductor core.

    Abstract translation: 描述了具有改进的门结构的电子设备的方法，系统和装置。 电子装置包括至少一个纳米线。 栅极接触沿至少一个纳米线的长度的至少一部分定位。 介电材料层在栅极接触和至少一个纳米线之间。 源极触点和漏极触点与至少一个纳米线接触。 源极触点和/或漏极触点的至少一部分沿着该纳米线的长度与栅极触点重叠。 另一方面，一种电子器件包括具有被绝缘壳层包围的半导体芯的纳米线。 环形第一栅极区域沿着纳米线长度的一部分包围纳米线。 第二栅极区沿着纳米线和衬底之间的纳米线的长度定位。 源极触点和漏极触点在半导体芯的相应的暴露部分处耦合到纳米线的半导体芯。

    WHITE POINT UNIFORMITY IN DISPLAY DEVICES
    5.
    发明申请
    WHITE POINT UNIFORMITY IN DISPLAY DEVICES 审中-公开
    显示设备中的白点均匀性

    公开(公告)号：WO2016168593A1

    公开(公告)日：2016-10-20

    申请号：PCT/US2016/027748

    申请日：2016-04-15

    Applicant: NANOSYS, INC.

    Inventor： CHEN, Jian ,  LEE, Ernest ,  WILSON, Robert E. ,  GENSLER, Steven

    IPC: G02F1/1335 ,  H01L33/50

    CPC classification number: G09G3/342 ,  G02B6/005 ,  G02B6/0073 ,  G02F1/133514 ,  G02F1/133606 ,  G02F1/133609 ,  G02F2001/133614 ,  G02F2202/36 ,  G09G3/32 ,  G09G2320/0233 ,  G09G2320/0242

    Abstract: Embodiments of a device and a method of tuning white point values of light distributed by a backlight unit (101) of a display device (200) are described. The device includes a backlight unit (101), an image generating unit (106), and a patterned layer (240). The backlight unit (101) includes a light source unit (102) and an optical processing unit (104) having a quantum dot film (114) coupled to the light source unit (102). The image generating unit (106) includes a display screen (126). The backlight unit (101) is configured to distribute light to the display screen (126) and the patterned layer (240) is configured to tune white point values of the distributed light to a desired white point value in order to achieve substantially uniform white point values across the display screen.

    Abstract translation: 描述了通过显示装置（200）的背光单元（101）分布的光调整白点值的装置和方法的实施例。 该装置包括背光单元（101），图像生成单元（106）和图案层（240）。 背光单元（101）包括具有耦合到光源单元（102）的量子点膜（114）的光源单元（102）和光学处理单元（104）。 图像生成单元（106）包括显示屏（126）。 背光单元（101）被配置为将光分配到显示屏（126）并且图案化层（240）被配置为将分布的光的白点值调谐到期望的白点值，以便实现基本均匀的白点 显示屏上的值。

    BACKLIGHT UNIT FOR DISPLAY DEVICES ADAPTED TO REDUCE LIGHT LEAKAGE
    6.
    发明申请
    BACKLIGHT UNIT FOR DISPLAY DEVICES ADAPTED TO REDUCE LIGHT LEAKAGE 审中-公开
    用于显示器件的背光单元适合减少光泄漏

    公开(公告)号：WO2015069640A1

    公开(公告)日：2015-05-14

    申请号：PCT/US2014/063871

    申请日：2014-11-04

    Applicant: NANOSYS, INC.

    Inventor： CHEN, Jian ,  GENSLER, Steven

    IPC: G02F1/1335

    CPC classification number: G02F1/133512 ,  F21V9/14 ,  G02B6/0023 ,  G02B6/005 ,  G02B6/0065 ,  G02B6/0073 ,  G02F1/0105 ,  G02F1/133603 ,  G02F1/133611 ,  G02F1/133615 ,  G02F2001/133388 ,  G02F2001/133614

    Abstract: Embodiments of a display device (300) and a method of reducing optical leakage from a backlight unit (202) of a display device (300) are described. The display device (300) includes a backlight unit (202, 208, 204), an image generating unit (206) coupled to the backlight unit and a blocking structure (334a-334e). The backlight unit (202, 208, 204) includes a light source unit (202) such as a blue LED and an optical processing unit (204) that comprises a quantum dot film (214) and optical sheets (222, 216). The backlight unit (202, 208, 204) is configured to transmit light to the image generating unit (206); the blocking structure (334a-334e) is configured to prevent the light from reaching the image generating unit without passing through the optical processing unit. The blocking structure (334a-334e) may consist of light-shielding tape, tabs or paint arranged along the periphery of the light guide plate (212), the optical sheets (22, 216) and the quantum dot film (214).

    Abstract translation: 描述了显示装置（300）的实施例和减少来自显示装置（300）的背光单元（202）的光泄漏的方法。 显示装置（300）包括背光单元（202,208,204），耦合到背光单元的图像生成单元（206）和阻挡结构（334a-334e）。 背光单元（202,208,204）包括诸如蓝色LED的光源单元（202）和包括量子点膜（214）和光学片（222,216）的光学处理单元（204）。 背光单元（202,208,204）被配置为向所述图像生成单元（206）发送光; 阻挡结构（334a-334e）被配置为防止光不经过光学处理单元到达图像生成单元。 阻挡结构（334a-334e）可以由沿着导光板（212）的周边，光学片（22,216）和量子点膜（214）布置的遮光带，突片或涂料组成。

    ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES
    8.
    发明申请
    ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES 审中-公开
    电子器件用电子封装层

    公开(公告)号：WO2010042323A1

    公开(公告)日：2010-04-15

    申请号：PCT/US2009/058182

    申请日：2009-09-24

    Applicant: NANOSYS, INC. ,  CHEN, Jian ,  SHARANGPANI, Rahul

    Inventor： CHEN, Jian ,  SHARANGPANI, Rahul

    IPC: H01L29/792

    CPC classification number: H01L29/42324 ,  B82Y10/00 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/66833

    Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

    Abstract translation: 描述诸如非易失性存储器件的电子设备的方法和装置。 存储器件包括多层控制电介质，例如双层或三层。 多层控制电介质包括高k电介质材料如氧化铝，氧化铪和/或铪铝氧化物的混合膜的组合。 多层控制电介质提供增强的特性，包括增加的电荷保留，增强的存储器程序/擦除窗口，改善的可靠性和稳定性，具有单一或多状态（例如，两个，三个或四个位）操作的可行性。

    METHODS FOR NANOSTRUCTURE DOPING
    9.
    发明申请
    METHODS FOR NANOSTRUCTURE DOPING 审中-公开

    公开(公告)号：WO2007038164A3

    公开(公告)日：2007-04-05

    申请号：PCT/US2006/036738

    申请日：2006-09-21

    Applicant: NANOSYS, INC. ,  PAN, Yaoling ,  CHEN, Jian ,  LEON, Francisco ,  MOSTARSHED, Shahriar ,  ROMANO, Linda T. ,  SAHI, Vijendra ,  STUMBO, David P.

    Inventor： PAN, Yaoling ,  CHEN, Jian ,  LEON, Francisco ,  MOSTARSHED, Shahriar ,  ROMANO, Linda T. ,  SAHI, Vijendra ,  STUMBO, David P.

    IPC: H01L29/06 ,  H01L21/225

    Abstract: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

    USE OF NANOPARTICLES IN FILM FORMATION AND AS SOLDER
    10.
    发明申请
    USE OF NANOPARTICLES IN FILM FORMATION AND AS SOLDER 审中-公开

    公开(公告)号：WO2006124625A3

    公开(公告)日：2006-11-23

    申请号：PCT/US2006/018480

    申请日：2006-05-12

    Applicant: NANOSYS, INC. ,  CHEN, Jian

    Inventor： CHEN, Jian

    IPC: B32B15/04

    Abstract: Nanoparticle compositions for use as solder, and methods for joining two or more material surfaces using nanoparticle solder compositions are described. Due to their small size, nanoparticles of a particular material have a lower melting temperature than the same material in bulk, thereby providing a homogenous bond between two or more materials when the nanoparticle solder is solidified. A gas species, such as hydrogen, can be introduced to further lower the melting temperature of the nanoparticles. The nanoparticles can also be used to form films on low melting point, substrates, including flexible substrates. The nanoparticles for use in the present invention can comprise any material, including semiconductor materials, metals, or insulator materials, and are less than about 20 nm in diameter, although larger sizes can also be used.

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