公开(公告)号：WO2017034714A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/043416

申请日：2016-07-21

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KAZI, Tauseef ,  ARTIERI, Alain Dominique

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203

Abstract: An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

Abstract translation: 集成电路设置有低功率岛，其包括嵌入式存储器电力域，其可选择性地耦合到在第一电力轨上提供的有源模式电源电压或提供在第二电力轨上的睡眠模式电源电压 。

公开(公告)号：WO2017019160A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/033910

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  BHAN, Divjyot ,  VILANGUDIPITCHAI, Ramaprasath ,  KUMAR, Dorav

IPC: H03K19/00

CPC classification number: H03K17/693 ,  H03K19/0016

Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.

Abstract translation: 本文公开了一种通过电力轨道复用进行电力管理的集成电路（IC）。 在示例方面，IC包括第一电源轨，第二电源轨和负载电源轨。 IC还包括第一组晶体管，其包括耦合到第一电力轨的第一晶体管和包括耦合到第二电力轨的第二晶体管的第二组晶体管。 IC还包括功率多路复用器电路，其被配置为通过顺序地关闭第一组晶体管的第一晶体管，然后顺序地导通第一组晶体管的第一晶体管，从而将负载电源轨从第一电力轨到第二电力轨的电​​力切换 第二组晶体管的第二晶体管。

公开(公告)号：WO2018004809A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/029669

申请日：2017-04-26

Applicant: QUALCOMM INCORPORATED

Inventor： WONG, Mong Chit ,  DANG, Nam ,  JAIN, Rajeev ,  SHAHROKHINIA, Sassan ,  HUANG, Yu ,  CAO, Lipeng

IPC: H02J1/10 ,  H02J1/08 ,  H02J9/06 ,  H01L23/50

Abstract: An integrated circuit (IC) is disclosed herein for adaptive power multiplexing with a power distribution network. In an example aspect, the integrated circuit includes a first power rail, a second power rail, and a load power rail. The integrated circuit also includes multiple power-multiplexer tiles and power-multiplexer control circuitry. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and configured to jointly perform a power-multiplexing operation. Each power-multiplexer tile is configured to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The power-multiplexer control circuitry is configured to control a direction of current flow to prevent cross-conduction between the first power rail and the second power rail during the power-multiplexing operation.

Abstract translation: 这里公开了一种用于与配电网络进行自适应功率复用的集成电路（IC）。 在一个示例方面中，集成电路包括第一电力轨道，第二电力轨道和负载电力轨道。 该集成电路还包括多个功率多路复用器片和功率多路复用器控制电路。 多个功率多路复用器瓦片以链接布置串联耦合并且被配置为共同执行功率多路复用操作。 每个功率多路复用器片被配置为在将负载电力轨耦合到第一电力轨并将负载电力轨耦合到第二电力轨之间切换。 功率多路复用器控制电路被配置为控制电流的方向以防止功率多路复用操作期间第一功率轨和第二功率轨之间的交叉传导。

公开(公告)号：WO2017116663A3

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：WO2017116663A2

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

Abstract translation: 这里公开了一种用于可调功率轨复用的集成电路（IC）。 在一个示例性方面，IC包括第一电源轨，第二电源轨和负载电源轨。 该IC还包括多个功率多路复用器（功率多路复用器）瓦片和调整电路。 多个功率多路复用器片以串联的方式串联耦合并且被实现为共同执行功率多路复用操作。 每个功率多路复用器瓦片被实现为在将负载电力轨耦合到第一电力轨并将负载电力轨耦合到第二电力轨之间切换。 调整电路被实现为调整多个功率多路复用片执行功率多路复用操作的至少一部分的至少一个顺序。

公开(公告)号：WO2017052838A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/046909

申请日：2016-08-12

Applicant: QUALCOMM INCORPORATED

Inventor： PANT, Harshat ,  VILANGUDIPITCHAI, Ramaprasath ,  BHAN, Divjyot ,  CAO, Lipeng ,  KOCHURI, Sai Pradeep ,  NAJDESAMII, Parissa

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/35625

Abstract: An integrated circuit (IC) is disclosed herein for managing power with flip-flops having a retention feature. In an example aspect, an IC includes a constant power rail (KPR), a collapsible power rail (CPR), multiple flip-flops (206), and power management circuitry (306). Each flip-flop (206) of the multiple flip-flops includes a master portion (302) that is coupled to the collapsible power rail (CPR) and a slave portion (304) that is coupled to the constant power rail (KPR). The power management circuitry (306) is configured to combine a clock signal (208) and a retention signal (210) into a combined control signal (CCS) and to provide the combined control signal to each flip-flop of the multiple flip-flops.

Abstract translation: 本文公开了一种用于通过具有保持特征的触发器来管理电力的集成电路（IC）。 在示例方面，IC包括恒定电力轨道（KPR），可折叠电力轨道（CPR），多个触发器（206）和电力管理电路（306）。 多个触发器的每个触发器（206）包括耦合到可折叠电源轨（CPR）的主部分（302）和耦合到恒功率轨道（KPR）的从部分（304）。 功率管理电路（306）被配置为将时钟信号（208）和保持信号（210）组合成组合控制信号（CCS），并将组合的控制信号提供给多个触发器的每个触发器 。

公开(公告)号：WO2021118719A1

公开(公告)日：2021-06-17

申请号：PCT/US2020/058946

申请日：2020-11-04

Applicant: QUALCOMM INCORPORATED

Inventor： SEVERSON, Matthew ,  ZOLEY, Timothy ,  CAO, Lipeng ,  CITTERELLE, Kevin Bradley ,  HOFMANN, Richard Gerard

IPC: G01R19/165

Abstract: An apparatus including a printed circuit board (PCB) including a sense resistor; and an integrated circuit (IC) mounted on the PCB, wherein at least a portion of the IC draws current from a power rail, wherein the sense resistor is coupled between the power rail and the IC, wherein the sense resistor is configured to produce a sense voltage in response to the current drawn by the at least portion of the IC, and wherein the IC includes a current sensor configured to generate a signal indicative of the current drawn by the at least portion of the IC based on the sense voltage.

公开(公告)号：WO2017200718A1

公开(公告)日：2017-11-23

申请号：PCT/US2017/029190

申请日：2017-04-24

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  BHAN, Divjyot ,  PANT, Harshat ,  VILANGUDIPITCHAI, Ramaprasath

IPC: H03K3/037 ,  G06F13/364 ,  G06F1/32 ,  H03K3/3562

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F13/364 ,  H03K3/0372 ,  H03K3/0375 ,  H03K3/3562 ,  H03K5/08 ,  Y02D10/171

Abstract: An integrated circuit (IC) is disclosed having a unified control scheme and a unifying architecture for different types of retention flip-flops (RFFs). In an example aspect, an IC includes a constant power rail to provide power during a power collapse period and a collapsible power rail to cease providing power during the power collapse period. The IC also includes a positive-edge-triggered (PET) RFF and a negative-edge-triggered (NET) RFF. The PET RFF includes a master portion and a slave portion, with the slave portion coupled to the constant power rail and the master portion coupled to the collapsible power rail. The NET RFF includes master and slave portions, with the master portion coupled to the constant power rail and the slave portion coupled to the collapsible power rail. In another example aspect, a control signal based on a clock and a retention signal may be routed to both RFFs.

Abstract translation: 公开了具有用于不同类型的保持触发器（RFF）的统一控制方案和统一架构的集成电路（IC）。 在一个示例方面，IC包括在功率崩溃时段期间提供功率的恒定功率导轨以及在功率崩溃时段期间停止提供功率的可折叠功率导轨。 该IC还包括一个正沿触发（PET）RFF和一个负沿触发（NET）RFF。 PET RFF包括主部分和从部分，其中从部分耦合到恒定功率轨道并且主部分耦合到可折叠功率轨道。 NET RFF包括主部分和从部分，其中主部分连接到恒定功率轨道，而从部分连接到可折叠功率轨道。 在另一个示例方面，基于时钟和保留信号的控制信号可以被路由到两个RFF。

公开(公告)号：WO2017052928A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048460

申请日：2016-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  GEMAR, Jeffrey ,  VILANGUDIPITCHAI, Ramaprasath

IPC: H03K3/356 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/0372 ,  H03K3/356008 ,  H03K3/3562

Abstract: Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

Abstract translation: 本文公开了诸如至少一个集成电路（IC）的数据保持电路，用于具有保留特征的触发器的功率复用。 在示例方面，IC包括第一电源轨和第二电源轨。 IC还包括触发器和功率复用电路。 触发器包括主部和从部。 主部分耦合到第一电力轨道用于常规操作模式和保持操作模式。 功率复用电路被配置为将从属部分耦合到用于常规操作模式的第一电力轨和用于保持操作模式的第二电力轨。