公开(公告)号：WO2018106372A1

公开(公告)日：2018-06-14

申请号：PCT/US2017/060213

申请日：2017-11-06

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Dorav ,  NARAYANAN, Venkat ,  ZAFAR, Bilal ,  RASOULI, Seid Hadi ,  BOYNAPALLI, Venugopal

IPC: G11C7/22 ,  G06F13/16

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.

公开(公告)号：WO2018057429A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/051835

申请日：2017-09-15

Applicant: QUALCOMM INCORPORATED

Inventor： ZAMANI, Masoud ,  ZAFAR, Bilal ,  NARAYANAN, Venkatasubramanian

IPC: G11C7/22

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract translation: 根据一些示例的存储器电路可以包括时钟延迟电路，该时钟延迟电路使用写入使能信号的极性来确定存储器上的提供期望的时钟等待时间的操作（即，写入或读取）到 记忆。 时钟延迟电路可以具有低歪斜部分和高歪斜部分。 高偏斜部分或低偏斜部分的选择可取决于写使能线的状态，例如极性或逻辑值。

公开(公告)号：WO2016043841A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/041194

申请日：2015-07-20

Applicant: QUALCOMM INCORPORATED

Inventor： BOYNAPALLI, Venugopal ,  BELLUR, Kashyap Ramachandra ,  BALU, Prabaharan ,  ZAFAR, Bilal ,  PARK, Alex Dongkyu ,  YOON, Sei Seung

IPC: G11C29/20 ,  G11C29/32

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.

Abstract translation: 示例性可扫描寄存器文件包括多个存储单元，并且扫描测试的移位阶段将数据位从通过多个存储单元的扫描输入移位到扫描输出。 可以通过在每个时钟周期读取多个存储器单元中的一个以提供扫描输出并将多个存储器单元中的一个与数据位一起写入扫描输入来执行移位。 为了在每个时钟周期执行顺序读和写操作，可扫描寄存器可以产生一个写时钟，在写入时钟期间，在移位阶段，与用于功能操作的时钟相反。 写时钟不产生毛刺，因此不会发生意外的写入。 可扫描寄存器文件可以集成在集成电路中的其他模块的基于扫描的测试（例如，使用自动测试模式生成）。

公开(公告)号：WO2015050786A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/057680

申请日：2014-09-26

Applicant: QUALCOMM INCORPORATED

Inventor： RAO, Hari ,  NARAYANAN, Venkatasubramanian ,  BOYNAPALLI, Venugopal ,  SABADE, Sagar Suresh ,  ZAFAR, Bilal

IPC: G06F11/27 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：WO2018048606A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/047764

申请日：2017-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： ZAFAR, Bilal ,  VATTIKONDA, Rakesh ,  LU, De ,  NARAYANAN, Venkatasubramanian ,  ZAMANI, Masoud ,  FANG, Joseph

IPC: G01R31/3185

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

Abstract translation: 在扫描捕获模式中采用互斥的写入和读取时钟来测试数字接口的装置和方法。 该装置包括第一电路和第一时钟发生器，被配置为在第一组扫描捕获周期中的每一个扫描捕获周期期间响应于第一时钟信号而生成用于将测试样本从输入传输到第一电路的输出的第一时钟信号 ; 第二电路和第二时钟发生器，被配置为在第二组扫描捕获周期中的每一个期间响应于第二时钟信号而生成用于将测试样本从输入传送到第二电路的输出的第二时钟信号; 第一时钟信号在第二组的每个扫描捕获周期期间被抑制，并且第二时钟信号在第一组的每个扫描捕获周期期间被抑制。

公开(公告)号：WO2017116663A3

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：WO2017116663A2

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

Abstract translation: 这里公开了一种用于可调功率轨复用的集成电路（IC）。 在一个示例性方面，IC包括第一电源轨，第二电源轨和负载电源轨。 该IC还包括多个功率多路复用器（功率多路复用器）瓦片和调整电路。 多个功率多路复用器片以串联的方式串联耦合并且被实现为共同执行功率多路复用操作。 每个功率多路复用器瓦片被实现为在将负载电力轨耦合到第一电力轨并将负载电力轨耦合到第二电力轨之间切换。 调整电路被实现为调整多个功率多路复用片执行功率多路复用操作的至少一部分的至少一个顺序。

公开(公告)号：WO2016073178A2

公开(公告)日：2016-05-12

申请号：PCT/US2015/056218

申请日：2015-10-19

Applicant: QUALCOMM INCORPORATED

Inventor： BOYNAPALLI, Venugopal ,  ZAFAR, Bilal

IPC: G11C29/00

CPC classification number: G11C29/70 ,  G11C11/419 ,  G11C29/765 ,  G11C29/808 ,  G11C29/886

Abstract: A cross-bar switch is provided that enables each master from a plurality of masters to read from and write to selected memories from an array of memories. A logic circuit controls the cross-bar switch so that redundancy for the memories is provided by a shared redundancy storage element.

Abstract translation: 提供了一种横杆开关，其使得来自多个主机的每个主机能够从存储器阵列中读取和写入所选择的存储器。 逻辑电路控制交叉开关，使得存储器的冗余由共享冗余存储元件提供。