公开(公告)号：WO2015089472A1

公开(公告)日：2015-06-18

申请号：PCT/US2014/070149

申请日：2014-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： GULATI, Chirag ,  AKHILESH, Ashish ,  NARAYANAN, Venkatasubramanian

IPC: G11C5/14 ,  G11C7/12 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C7/12

Abstract: A memory device biasing circuit is disclosed, the circuit having a pair of semiconductor devices coupled to receive a supply voltage having a supply voltage level suitable for operating a memory device in an active mode and operable for providing an adjustable biased voltage to the memory device that is greater than a minimal voltage level for operating the memory device in a data retention mode. The pair of semiconductor devices includes a first semiconductor device; and, a second semiconductor device that includes an opposite type of semiconductor device than the first semiconductor device such that the pair of semiconductor devices includes each of an N-type semiconductor device and a P-type semiconductor device. The memory device biasing circuit further includes a bias adjustment circuit coupled to the second semiconductor device and configured to adjust the operation of the second semiconductor device based on the supply voltage.

Abstract translation: 公开了一种存储器件偏置电路，该电路具有一对半导体器件，其被耦合以接收电源电压，该电源电压具有适于在有源模式下操作存储器件的电源电压电平，并可操作以向存储器件提供可调节的偏置电压， 大于在数据保持模式下操作存储器件的最小电压电平。 所述一对半导体器件包括第一半导体器件; 以及包括与第一半导体器件相反的半导体器件的第二半导体器件，使得该对半导体器件包括N型半导体器件和P型半导体器件中的每一个。 存储器件偏置电路还包括耦合到第二半导体器件并被配置为基于电源电压来调整第二半导体器件的操作的偏置调整电路。

公开(公告)号：WO2018048606A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/047764

申请日：2017-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： ZAFAR, Bilal ,  VATTIKONDA, Rakesh ,  LU, De ,  NARAYANAN, Venkatasubramanian ,  ZAMANI, Masoud ,  FANG, Joseph

IPC: G01R31/3185

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

Abstract translation: 在扫描捕获模式中采用互斥的写入和读取时钟来测试数字接口的装置和方法。 该装置包括第一电路和第一时钟发生器，被配置为在第一组扫描捕获周期中的每一个扫描捕获周期期间响应于第一时钟信号而生成用于将测试样本从输入传输到第一电路的输出的第一时钟信号 ; 第二电路和第二时钟发生器，被配置为在第二组扫描捕获周期中的每一个期间响应于第二时钟信号而生成用于将测试样本从输入传送到第二电路的输出的第二时钟信号; 第一时钟信号在第二组的每个扫描捕获周期期间被抑制，并且第二时钟信号在第一组的每个扫描捕获周期期间被抑制。

公开(公告)号：WO2017116663A3

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

公开(公告)号：WO2017116663A2

公开(公告)日：2017-07-06

申请号：PCT/US2016/066102

申请日：2016-12-12

Applicant: QUALCOMM INCORPORATED

Inventor： CAO, Lipeng ,  KUMAR, Dorav ,  ZAFAR, Bilal ,  VILANGUDIPITCHAI, Ramaprasath ,  NARAYANAN, Venkatasubramanian ,  LUO, Xi

IPC: H03K19/00

CPC classification number: H01H47/00 ,  H03K19/0008

Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power mux tiles perform at least a portion of the power-multiplexing operation.

Abstract translation: 这里公开了一种用于可调功率轨复用的集成电路（IC）。 在一个示例性方面，IC包括第一电源轨，第二电源轨和负载电源轨。 该IC还包括多个功率多路复用器（功率多路复用器）瓦片和调整电路。 多个功率多路复用器片以串联的方式串联耦合并且被实现为共同执行功率多路复用操作。 每个功率多路复用器瓦片被实现为在将负载电力轨耦合到第一电力轨并将负载电力轨耦合到第二电力轨之间切换。 调整电路被实现为调整多个功率多路复用片执行功率多路复用操作的至少一部分的至少一个顺序。

公开(公告)号：WO2014022416A1

公开(公告)日：2014-02-06

申请号：PCT/US2013/052758

申请日：2013-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： NARAYANAN, Venkatasubramanian ,  BELLUR, Kashyap R.

IPC: G11C29/32

CPC classification number: H03K3/356 ,  G06F17/5045 ,  G11C29/32

Abstract: A system and method to perform scan testing using a pulse latch with a blocking gate is disclosed. In a particular embodiment, a scan latch includes a pulse latch operable to receive data while a pulse clock signal has a first logical clock value and a blocking gate coupled to an output of the pulse latch. The blocking gate is operable to propagate the data from the output of the pulse latch while the pulse clock signal has a second logical clock value.

Abstract translation: 公开了一种使用具有阻塞门的脉冲锁存器执行扫描测试的系统和方法。 在特定实施例中，扫描锁存器包括可操作以在脉冲时钟信号具有第一逻辑时钟值并且耦合到脉冲锁存器的输出的阻塞栅极时接收数据的脉冲锁存器。 阻塞门可操作以在脉冲时钟信号具有第二逻辑时钟值的同时从脉冲锁存器的输出传播数据。

公开(公告)号：WO2019013925A1

公开(公告)日：2019-01-17

申请号：PCT/US2018/037778

申请日：2018-06-15

Applicant: QUALCOMM INCORPORATED

Inventor： NARAYANAN, Venkatasubramanian ,  KUMAR, Dorav ,  VILANGUDIPITCHAI, Ramaprasath ,  BOYNAPALLI, Venugopal

IPC: G06F1/26 ,  G06F1/32 ,  G11C16/30 ,  H03K19/00 ,  H02J1/06 ,  H03K17/06 ,  H03K17/687 ,  H03K17/693

Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.

公开(公告)号：WO2017222638A1

公开(公告)日：2017-12-28

申请号：PCT/US2017/029700

申请日：2017-04-26

Applicant: QUALCOMM INCORPORATED

Inventor： KUMAR, Dorav ,  NARAYANAN, Venkatasubramanian ,  THALLA, Bala Krishna ,  RASOULI, Seid Hadi ,  GUTTAL, Radhika Vinayak ,  PATURI, Sivakumar

IPC: H01L23/528 ,  H03K19/177

Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a M x layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the M x layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a M y layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the M y layer that is coupled to the second output on the fifth track.

Abstract translation: MOS器件可以包括具有位于第二轨道上的第一输入端和位于第三轨道上的第一输出端的第一逻辑组件。 MOS器件可以包括具有位于第四轨道上的第二输入端和位于第五轨道上的第二输出端的第二逻辑组件。 例如，MOS器件包括耦合到第二轨道上的第一输入的Mx层上的第一互连。 在另一个示例中，MOS器件包括在第三轨道上耦合到第一输出的Mx层上的第二互连。 MOS器件包括耦合到第四轨道上的第二输入的M y层上的第三互连。 更进一步地，MOS器件包括在第五轨道上耦合到第二输出的第M层上的第四互连。

公开(公告)号：WO2017142696A1

公开(公告)日：2017-08-24

申请号：PCT/US2017/015565

申请日：2017-01-30

Applicant: QUALCOMM INCORPORATED

Inventor： YE, Qi ,  DATTA, Animesh ,  NARAYANAN, Venkatasubramanian ,  BOYNAPALLI, Venugopal

IPC: H03K3/033 ,  H03K5/04

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

Abstract translation: 该装置可以包括被配置为存储第一状态或第二状态的第一锁存器。 第一锁存器可具有第一锁存器输入，置位输入或复位输入，第一脉冲时钟输入和第一锁存器输出中的一个。 第一锁存器输入可以耦合到固定的逻辑值。 置位输入或复位输入中的一个可分别耦合到时钟信号或反相时钟信号。 该装置可以包括具有第一与门输入，第二与门输入和第一与门输出的与门。 时钟信号可以耦合到第一与门输入。 第一锁存器输出可以耦合到第二与门输入。 与门输出可以被配置为输出脉冲时钟。 脉冲时钟可以耦合到第一脉冲时钟输入。

公开(公告)号：WO2018057429A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/051835

申请日：2017-09-15

Applicant: QUALCOMM INCORPORATED

Inventor： ZAMANI, Masoud ,  ZAFAR, Bilal ,  NARAYANAN, Venkatasubramanian

IPC: G11C7/22

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

Abstract translation: 根据一些示例的存储器电路可以包括时钟延迟电路，该时钟延迟电路使用写入使能信号的极性来确定存储器上的提供期望的时钟等待时间的操作（即，写入或读取）到 记忆。 时钟延迟电路可以具有低歪斜部分和高歪斜部分。 高偏斜部分或低偏斜部分的选择可取决于写使能线的状态，例如极性或逻辑值。

公开(公告)号：WO2016191046A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/030448

申请日：2016-05-02

Applicant: QUALCOMM INCORPORATED

Inventor： NARAYANAN, Venkatasubramanian ,  PARK, Alex Dongkyu

IPC: G11C29/04 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C11/417 ,  G11C11/419 ,  G11C29/04 ,  G11C29/12005 ,  G11C29/50004 ,  G11C2029/0401 ,  G11C2029/1204 ,  H01L27/1116

Abstract: A static random access memory (SRAM) includes a first bitcell and a second bitcell. The first bitcell includes an aging transistor and the second bitcell includes a non-aging transistor. An aging sensor is coupled between the first bitcell and the second bitcell to determine an amount of aging associated with the aging transistor. In one aspect, the amount of aging associated with the aging transistor is determined based on a difference between a voltage or current associated with the aging transistor and a voltage or current associated with the non-aging transistor.

Abstract translation: 静态随机存取存储器（SRAM）包括第一位单元和第二位单元。 第一位单元包括老化晶体管，第二位单元包括非老化晶体管。 老化传感器耦合在第一位单元和第二位单元之间以确定与老化晶体管相关联的老化量。 在一个方面，与老化晶体管相关联的老化量基于与老化晶体管相关联的电压或电流与与非老化晶体管相关联的电压或电流之间的差来确定。