公开(公告)号：WO2018044482A1

公开(公告)日：2018-03-08

申请号：PCT/US2017/045081

申请日：2017-08-02

Applicant: QUALCOMM INCORPORATED

Inventor： JAIN, Kunal ,  GHOSH, Moitrayee ,  BHAT, Anand ,  FANG, Joseph

IPC: G06F1/10 ,  G01R31/3187 ,  G06F1/32

Abstract: Segregated test mode clock gating circuits in a clock distribution network of a circuit for controlling power consumption during testing is provided. To reduce power consumption and current-resistance (IR) drop during testing of a circuit, existing clock gating circuits (e.g., clock gating cells (CGCs)) that control the functional mode of circuit blocks in the circuit are additionally test mode gated for hierarchical testing of the circuit. To avoid the need to gate every CGC in the clock distribution network, only certain segregated clock gating circuits in the clock distribution network may be selected for test mode clock gating according to desired testing hierarchy of the circuit. Test mode clock gating of only certain segregated clock gating circuits in a circuit can reduce the number of test gating circuits providing test mode clock gating to mitigate power consumption and area needed for providing selective testing of circuit blocks in the circuit.

Abstract translation: 提供了用于控制测试期间的功耗的电路的时钟分配网络中的分离的测试模式时钟门控电路。 为了降低电路测试期间的功耗和电流阻抗（IR）下降，控制电路中电路模块的功能模式的现有时钟门控电路（例如，时钟门控单元（CGC））另外被测试模式门控 电路测试。 为了避免需要对时钟分配网络中的每个CGC进行选通，根据期望的电路测试层次，可以仅选择时钟分配网络中的某些分离时钟选通电路用于测试模式时钟选通。 测试模式时钟门控电路中的某些分离时钟门控电路可以减少提供测试模式时钟门控的测试门控电路的数量，以减少为电路中的电路模块提供选择性测试所需的功耗和面积。

公开(公告)号：WO2018048606A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/047764

申请日：2017-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： ZAFAR, Bilal ,  VATTIKONDA, Rakesh ,  LU, De ,  NARAYANAN, Venkatasubramanian ,  ZAMANI, Masoud ,  FANG, Joseph

IPC: G01R31/3185

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

Abstract translation: 在扫描捕获模式中采用互斥的写入和读取时钟来测试数字接口的装置和方法。 该装置包括第一电路和第一时钟发生器，被配置为在第一组扫描捕获周期中的每一个扫描捕获周期期间响应于第一时钟信号而生成用于将测试样本从输入传输到第一电路的输出的第一时钟信号 ; 第二电路和第二时钟发生器，被配置为在第二组扫描捕获周期中的每一个期间响应于第二时钟信号而生成用于将测试样本从输入传送到第二电路的输出的第二时钟信号; 第一时钟信号在第二组的每个扫描捕获周期期间被抑制，并且第二时钟信号在第一组的每个扫描捕获周期期间被抑制。