公开(公告)号：WO2015163990A1

公开(公告)日：2015-10-29

申请号：PCT/US2015/020217

申请日：2015-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： JUNG, Changho ,  GUO, Frank ,  VATTIKONDA, Rakesh

IPC: H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/356182

Abstract: A level-shifter is provided with PMOS stacks that are selectively weakened or strengthened depending upon the binary state of an input signal.

Abstract translation: 电平移位器具有根据输入信号的二进制状态选择性地削弱或加强的PMOS堆叠。

公开(公告)号：WO2019164627A1

公开(公告)日：2019-08-29

申请号：PCT/US2019/014858

申请日：2019-01-24

Applicant: QUALCOMM INCORPORATED

Inventor： RAMARAJU, Ravindraraj ,  VATTIKONDA, Rakesh ,  SINHAROY, Samrat ,  LU, De ,  PANG, Bo

IPC: H04L9/00

Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

公开(公告)号：WO2018013299A1

公开(公告)日：2018-01-18

申请号：PCT/US2017/038347

申请日：2017-06-20

Applicant: QUALCOMM INCORPORATED

Inventor： VATTIKONDA, Rakesh ,  SINHAROY, Samrat ,  LU, De

IPC: G01R31/3185 ,  H03K3/037

CPC classification number: H03K3/0372 ,  G01R31/31704 ,  G01R31/31723 ,  G01R31/318541

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

Abstract translation: 在本公开的一个方面中，提供了一种方法和装置。 该装置是包括第一和第二触发器锁存器阵列的寄存器阵列。 第一触发器锁存器阵列包括第一组主锁存器，耦合到第一组主锁存器的第一组从锁存器以及第一地址端口。 第二触发器锁存器阵列包括第二组主锁存器，耦合到第二组主锁存器的第二组从锁存器以及第二地址端口。 寄存器阵列包括耦合到第一触发器锁存器阵列和第二触发器锁存器阵列的地址计数器。 地址计数器由第一触发器锁存器阵列和第二触发器锁存器阵列共享，并被配置为通过第一地址端口和第二触发器锁存器阵列并行地在测试模式下寻址第一触发器锁存器阵列， 通过第二个地址端口触发锁存器阵列。

公开(公告)号：WO2015163992A1

公开(公告)日：2015-10-29

申请号：PCT/US2015/020579

申请日：2015-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： JUNG, Changho ,  VATTIKONDA, Rakesh ,  KWOK, Tony Chung Yiu

IPC: G11C5/14 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  G11C11/417

CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C7/18 ,  G11C8/16 ,  G11C11/417

Abstract: A memory and a method for operating the memory having a sleep mode are provided. The memory one or more storage elements and a bitline coupled to the one or more storage elements. A precharge circuit is configured to precharge the bitline during a precharge period and float the bitline during a sleep mode. An operating circuit coupled to the one or more storage elements, wherein at least one of the operating circuit and the one or more storage elements being configured to remain electrically coupled to a supply voltage in the sleep mode.

Abstract translation: 提供了一种用于操作具有休眠模式的存储器的存储器和方法。 存储器一个或多个存储元件和耦合到一个或多个存储元件的位线。 预充电电路被配置为在预充电周期期间预充电位线，并且在睡眠模式期间浮动位线。 耦合到所述一个或多个存储元件的操作电路，其中所述操作电路和所述一个或多个存储元件中的至少一个被配置为在睡眠模式下保持电耦合到电源电压。

公开(公告)号：WO2018048606A1

公开(公告)日：2018-03-15

申请号：PCT/US2017/047764

申请日：2017-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： ZAFAR, Bilal ,  VATTIKONDA, Rakesh ,  LU, De ,  NARAYANAN, Venkatasubramanian ,  ZAMANI, Masoud ,  FANG, Joseph

IPC: G01R31/3185

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.

Abstract translation: 在扫描捕获模式中采用互斥的写入和读取时钟来测试数字接口的装置和方法。 该装置包括第一电路和第一时钟发生器，被配置为在第一组扫描捕获周期中的每一个扫描捕获周期期间响应于第一时钟信号而生成用于将测试样本从输入传输到第一电路的输出的第一时钟信号 ; 第二电路和第二时钟发生器，被配置为在第二组扫描捕获周期中的每一个期间响应于第二时钟信号而生成用于将测试样本从输入传送到第二电路的输出的第二时钟信号; 第一时钟信号在第二组的每个扫描捕获周期期间被抑制，并且第二时钟信号在第一组的每个扫描捕获周期期间被抑制。

公开(公告)号：WO2014123757A1

公开(公告)日：2014-08-14

申请号：PCT/US2014/013920

申请日：2014-01-30

Applicant: QUALCOMM INCORPORATED

Inventor： JUNG, Changho ,  DESAI, Nishith ,  VATTIKONDA, Rakesh

IPC: G11C11/419

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/00 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/419

Abstract: A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddM lower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP ≥ VddM > VddM lower .

Abstract translation: 提供一种写辅助驱动器电路，即使当电源电压降低时，也可以在写入操作中帮助存储器单元（例如，易失性存储器位单元）来保持存储器核心处的电压足够高以用于正确的写入操作。 写辅助驱动器电路可以被配置为在待机操作模式期间向位单元核提供存储器电源电压VddM。 在写入操作模式中，写入辅助驱动器电路可以向位单元核心以及本地写入位线（lwbl）和本地写入位线条（lwblb）中的至少一个提供降低的存储器电源电压VddMlower。 此外，写入辅助驱动器电路还可以向本地写入字线（lww1）提供外围电源电压VddP，其中VddP≥VddM> VddMlower。

公开(公告)号：WO2014105683A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/076848

申请日：2013-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： TERZIOGLU, Esin ,  DESAI, Nishith ,  VATTIKONDA, Rakesh ,  JUNG, ChangHo ,  YOON, Sei Seung

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：WO2018005086A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/037338

申请日：2017-06-13

Applicant: QUALCOMM INCORPORATED

Inventor： NARAYANAN, Venkat ,  VATTIKONDA, Rakesh ,  LU, De ,  VILANGUDIPITCHAI, Ramaprasath ,  SINHAROY, Samrat ,  CHEN, Rui

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/096

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter (810) includes a first p-type metal-oxide-semiconductor transistor (835) having a gate configured to receive an input signal (D) in a first power domain, and a second PMOS transistor (840), wherein the first and second PMOS transistors are coupled in series between a supply voltage (vddout) of a second power domain and a node (820). The voltage level shifter also includes an inverter (850) having an input coupled to the node and an output (Z) coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor transistor (830) having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

Abstract translation: 在一个实施例中，电压电平移位器（810）包括第一p型金属氧化物半导体晶体管（835），其具有被配置为接收第一功率 域和第二PMOS晶体管（840），其中第一和第二PMOS晶体管串联耦合在第二电源域的电源电压（vddout）和节点（820）之间。 电压电平移位器还包括反相器（850）和第一n型金属氧化物半导体晶体管（830），第一n型金属氧化物半导体晶体管（830）具有耦合到节点的输入和耦合到第二PMOS晶体管的栅极的输出（Z） 栅极，被配置为在第一电源域中接收输入信号，其中第一NMOS晶体管耦合在节点和地之间。

公开(公告)号：WO2018005085A1

公开(公告)日：2018-01-04

申请号：PCT/US2017/037335

申请日：2017-06-13

Applicant: QUALCOMM INCORPORATED

Inventor： NARAYANAN, Venkat ,  VATTIKONDA, Rakesh ,  LU, De ,  VILANGUDIPITCHAI, Ramaprasath ,  SINHAROY, Samrat ,  CHEN, Rui

IPC: H03K3/012 ,  H03K3/356

Abstract: A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second power domain, a third input (257), and an output (Z). The voltage level shifter also includes a second NOR gate (220) having a first input (222) configured to receive a second input signal (D) in the first power domain, a second input (225) configured to receive the enable signal in the second power domain, a third input (227) coupled to the output of the first NOR gate, and an output (Z_N) coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

Abstract translation: 电压电平移位器包括具有被配置为在第一电力域中接收第一输入信号（D_N）的第一输入端（252）的第一或非门（250），被配置为在第一输入端 以在第二电力域，第三输入（257）和输出（Z）中接收使能信号（ENB）。 所述电压电平移位器还包括第二NOR门（220），所述第二NOR门具有被配置为在所述第一电力域中接收第二输入信号（D）的第一输入（222），被配置为在所述第一电力域中接收所述使能信号 第二电源域，耦合到第一或非门的输出的第三输入（227）以及耦合到第一或非门的第三输入的输出（Z_N）。 第一和第二NOR门由第二电源域的电源供电。

公开(公告)号：WO2014105684A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/076853

申请日：2013-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： VATTIKONDA, Rakesh ,  DESAI, Nishith ,  JUNG, ChangHo ,  YOON, Sei Seung ,  TERZIOGLU, Esin

IPC: G11C15/04

CPC classification number: G11C15/00 ,  G11C15/04

Abstract: A method within a hybrid ternary content addressable memory (TCAM) includes comparing a first portion of a search word to a first portion of a stored word in a first TCAM stage. The method further includes interfacing an output of the first TCAM stage to an input of the second TCAM stage. The method also includes comparing a second portion of the search word to a second portion of the stored word in a second TCAM stage when the first portion of the search word matches the first portion of the stored word. The first TCAM stage is different from the second TCAM stage.

Abstract translation: 混合三元内容可寻址存储器（TCAM）内的方法包括将搜索词的第一部分与第一TCAM级中的存储字的第一部分进行比较。 该方法还包括将第一TCAM级的输出与第二TCAM级的输入进行接口。 该方法还包括当搜索词的第一部分与存储的单词的第一部分匹配时，在第二TCAM阶段中将搜索词的第二部分与所存储的单词的第二部分进行比较。 第一个TCAM阶段与第二个TCAM阶段不同。