公开(公告)号：WO2016085641A1

公开(公告)日：2016-06-02

申请号：PCT/US2015/059677

申请日：2015-11-09

Applicant: QUALCOMM INCORPORATED

Inventor： HOWER, Derek, Robert ,  CAIN, III, Harold, Wade

IPC: G06F12/08 ,  G06F12/12 ,  G06F11/34

CPC classification number: G06F12/084 ,  G06F11/34 ,  G06F12/0833 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/314 ,  G06F2212/6042 ,  G06F2212/62

Abstract: Providing shared cache memory allocation control in shared cached memory systems is disclosed. In one aspect, a cache controller of a shared cache memory system comprising a plurality of cache lines is provided. The cache controller comprises a cache allocation circuit providing a minimum mapping bitmask for mapping a Quality of Service (QoS) class to a minimum partition of the cache lines, and a maximum mapping bitmask for mapping the QoS class to a maximum partition of the cache lines. The cache allocation circuit receives a memory access request comprising a QoS identifier (QoSID) of the QoS class, and is configured to determine whether the memory access request corresponds to a cache line of the plurality of cache lines. If not, the cache allocation circuit selects, as a target partition, the minimum partition mapped to the QoS class or the maximum partition mapped to the QoS class.

Abstract translation: 公开了在共享缓存存储器系统中提供共享缓存存储器分配控制。 在一个方面，提供了包括多个高速缓存行的共享高速缓冲存储器系统的高速缓存控制器。 高速缓存控制器包括高速缓存分配电路，其提供用于将服务质量（QoS）类映射到高速缓存行的最小分区的最小映射位掩码，以及用于将QoS类映射到高速缓存行的最大分区的最大映射位掩码 。 高速缓存分配电路接收包括QoS类别的QoS标识符（QoSID）的存储器访问请求，并且被配置为确定存储器访问请求是否对应于多个高速缓存行的高速缓存行。 如果不是，则高速缓存分配电路选择映射到QoS类或映射到QoS类的最大分区的最小分区作为目标分区。

公开(公告)号：WO2016085642A1

公开(公告)日：2016-06-02

申请号：PCT/US2015/059685

申请日：2015-11-09

Applicant: QUALCOMM INCORPORATED

Inventor： HOWER, Derek, Robert ,  CAIN, III, Harold, Wade

IPC: G06F12/08 ,  G06F11/34

CPC classification number: G06F12/084 ,  G06F11/3037 ,  G06F11/3433 ,  G06F11/3466 ,  G06F11/3471 ,  G06F11/348 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/2112 ,  G06F2212/282 ,  G06F2212/314 ,  Y02D10/13

Abstract: Generating approximate usage measurements for shared cache memory systems is disclosed. In one aspect, a cache memory system is provided. The cache memory system comprises a shared cache memory system. A subset of the shared cache memory system comprises a Quality of Service identifier (QoSID) tracking tag configured to store a QoSID tracking indicator for a QoS class. The shared cache memory system further comprises a cache controller configured to receive a memory access request comprising a QoSID, and is configured to access a cache line corresponding to the memory access request. The cache controller is also configured to determine whether the QoSID of the memory access request corresponds to a cache line assigned to the QoSID. If so, the cache controller is additionally configured to update the QoSID tracking tag.

Abstract translation: 公开了为共享高速缓冲存储器系统生成近似使用测量值。 一方面，提供一种高速缓冲存储器系统。 高速缓冲存储器系统包括共享高速缓冲存储器系统。 共享高速缓冲存储器系统的子集包括服务质量标识符（QoSID）跟踪标签，其被配置为存储用于QoS类别的QoSID跟踪指示符。 共享高速缓冲存储器系统还包括高速缓存控制器，其被配置为接收包括QoSID的存储器访问请求，并且被配置为访问对应于存储器访问请求的高速缓存行。 高速缓存控制器还被配置为确定存储器访问请求的QoSID是否对应于分配给QoSID的高速缓存行。 如果是这样，高速缓存控制器被配置为更新QoSID跟踪标签。

公开(公告)号：WO2019055598A1

公开(公告)日：2019-03-21

申请号：PCT/US2018/050805

申请日：2018-09-13

Applicant: QUALCOMM INCORPORATED

Inventor： PRIYADARSHI, Shivam ,  ZAHEDI, SeyedMajid ,  HOWER, Derek, Robert ,  WALDSPURGER, Carl, Alan ,  BRIDGES, Jeffrey, Todd ,  PATEL, Sanjay, Bhikhubhai ,  TARR, Gabriel, Martel ,  LIN, Chih, Kang ,  WELLS, Ryan, Donovan ,  CAIN, III, Harold, Wade

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296

Abstract: Allocating power between multiple central processing units (CPUs) in a multi-CPU processor based on total current availability and individual CPU quality-of-service (QoS) requirements is disclosed. Current from a power rail is allocated to CPUs by a global current manger (GCM) circuit related to performance criteria set by CPUs. The CPUs can request increased current allocation from the GCM circuit, such as in response to executing a higher performance task. If the increased current allocation request keeps total current on the power rail within its maximum rail current limit, the GCM circuit approves the request to allow the CPU increased current allocation. This can allow CPUs executing higher performance tasks to have a larger current allocation than CPUs executing lower performance tasks without the maximum rail current limit being exceeded, and without having to necessarily lower voltage of the power rail, which could unnecessarily lower performance of all CPUs.

公开(公告)号：WO2019045954A1

公开(公告)日：2019-03-07

申请号：PCT/US2018/045370

申请日：2018-08-06

Applicant: QUALCOMM INCORPORATED

Inventor： HOWER, Derek, Robert ,  WALDSPURGER, Carl, Alan ,  SETHI, Vikramjit

IPC: G06F12/0842 ,  G06F9/50

Abstract: Providing fine-grained Quality of Service (QoS) control using interpolation for partitioned resources in processor-based systems is disclosed. In this regard, in one aspect, a processor-based system provides a partitioned resource (such as a system cache or memory access bandwidth to a shared system memory) that is subdivided into a plurality of partitions, and that is configured to service a plurality of resource clients. A resource allocation agent of the processor-based system provides a plurality of allocation indicators corresponding to each combination of resource client and partition, and indicating an allocation of each partition for each resource client. The resource allocation agent allocates the partitioned resource among the resource clients based on an interpolation of the plurality of allocation indicators. Because each allocation indicator may be different for each combination of resource client and partition, interpolation of the allocation indicators provides a higher-resolution aggregate resource allocation for each resource client.