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    LOW POWER OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
    1.
    发明申请
    LOW POWER OPERATIONAL TRANSCONDUCTANCE AMPLIFIER 审中-公开
    低功率运行的交叉放大器

    公开(公告)号：WO2016099757A1

    公开(公告)日：2016-06-23

    申请号：PCT/US2015/061163

    申请日：2015-11-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIRAN, Ganesh

    IPC: H03F3/45 ,  H03F3/195 ,  H03F3/24

    CPC classification number: H03F1/0205 ,  H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45288 ,  H03F2203/45364 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03H11/0427 ,  H03H19/004

    Abstract: A low power operational transconductance amplifier is disclosed. In an exemplary embodiment, an apparatus includes a transconductance stage (402) configured to convert a first input voltage signal (Vil) to first and second current signals and to convert a second input voltage signal (Vi2) to third and fourth current signals. The apparatus also includes a current amplification stage (404) configured to amplify the second current signal to generate a first amplified current signal and to amplify the fourth current signal to generate a second amplified current signal. The apparatus also includes a current summation stage (406) configured to sum together the third current signal and the first amplified current signal to generate a first output voltage signal (Vol), and to sum together the first current signal and the second amplified current signal to generate a second output voltage signal (Vo2).

    Abstract translation: 公开了一种低功率运算跨导放大器。 在示例性实施例中，一种装置包括跨导级（402），其构造成将第一输入电压信号（Vil）转换为第一和第二电流信号，并将第二输入电压信号（Vi2）转换为第三和第四电流信号。 该装置还包括电流放大级（404），其被配置为放大第二电流信号以产生第一放大电流信号并放大第四电流信号以产生第二放大电流信号。 该装置还包括电流求和级（406），其被配置为将第三电流信号和第一放大电流信号相加在一起以产生第一输出电压信号（Vol），并将第一电流信号和第二放大电流信号 以产生第二输出电压信号（Vo2）。

    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH TIME-INTERLEAVED (TI) OR TWO-STEP SUCCESSIVE APPROXIMATION REGISTER (SAR) QUANTIZER
    2.
    发明申请
    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER (ADC) WITH TIME-INTERLEAVED (TI) OR TWO-STEP SUCCESSIVE APPROXIMATION REGISTER (SAR) QUANTIZER 审中-公开
    具有时间间隔（TI）或两步逐次逼近寄存器（SAR）量子的DELTA-SIGMA模拟到数字转换器（ADC）

    公开(公告)号：WO2017052921A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/048394

    申请日：2016-08-24

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAJAEE, Omid ,  HAN, Changsok ,  DAI, Liang ,  MIRHAJ, Seyed Arash ,  KIRAN, Ganesh

    IPC: H03M3/00 ,  H03M1/46 ,  H03M1/10

    CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

    Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

    Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用增加的采样率。

    SEGMENTED SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH REDUCED CONVERSION TIME
    3.
    发明申请
    SEGMENTED SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTER (ADC) WITH REDUCED CONVERSION TIME 审中-公开
    具有降低转换时间的分段后续的近似寄存器（SAR）模数转换器（ADC）

    公开(公告)号：WO2017053028A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/049396

    申请日：2016-08-30

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAJAEE, Omid ,  DAI, Liang ,  KIRAN, Ganesh

    IPC: H03M1/18 ,  H03M1/10 ,  H03M1/38

    CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

    Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

    Abstract translation: 本公开的某些方面提供了分段逐次逼近寄存器（SAR）模数转换器（ADC）。 一个示例性ADC通常包括多个SAR ADC电路，每个与ADC的电压范围的不同电压范围段相关联。 每个SAR ADC电路被配置为接收输入到ADC的模拟信号并且基于模拟信号输出数字信号，当模拟信号的电压电平在...之内时，数字信号代表模拟信号的电压电平 与SAR ADC电路相关的分段。 在某些方面，SAR ADC可以包括被配置为基于代表由多个SAR ADC电路中的一个或多个输出的模拟信号的电压电平的一个或多个数字信号来控制ADC的数字输出的逻辑。

    OUTPUT COMMON-MODE CONTROL FOR DYNAMIC AMPLIFIERS
    4.
    发明申请
    OUTPUT COMMON-MODE CONTROL FOR DYNAMIC AMPLIFIERS 审中-公开

    公开(公告)号：WO2023023450A1

    公开(公告)日：2023-02-23

    申请号：PCT/US2022/074539

    申请日：2022-08-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： AKHAVAN, Aram ,  YAMAMOTO, Kentaro ,  SUN, Lei ,  KIRAN, Ganesh

    IPC: H03F3/45 ,  H03F3/72

    Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

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