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    REDUCING SIGNAL DEPENDENCE FOR CDAC REFERENCE VOLTAGE
    1.
    发明申请
    REDUCING SIGNAL DEPENDENCE FOR CDAC REFERENCE VOLTAGE 审中-公开
    降低CDAC参考电压信号依赖性

    公开(公告)号：WO2016029050A1

    公开(公告)日：2016-02-25

    申请号：PCT/US2015/046161

    申请日：2015-08-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： MIRHAJ, Seyed Arash ,  WADHWA, Sameer ,  ALLADI, Dinesh Jagannath ,  YAMAMOTO, Kentaro ,  WEN, Xiaoke ,  ENSAFDARAN, Masoud ,  CHEN, Weihua

    IPC: H03M1/06

    CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

    Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

    Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。

    ALIAS REJECTION THROUGH CHARGE SHARING
    2.
    发明申请
    ALIAS REJECTION THROUGH CHARGE SHARING 审中-公开

    公开(公告)号：WO2019125678A1

    公开(公告)日：2019-06-27

    申请号：PCT/US2018/061647

    申请日：2018-11-16

    Applicant: QUALCOMM INCORPORATED

    Inventor： BAKER, Sean ,  ALLADI, Dinesh Jagannath ,  SIVAKUMAR, Balasubramanian ,  YAMAMOTO, Kentaro

    IPC: H03M1/06 ,  H03M1/46

    Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

    LOW NOISE AND LOW POWER PASSIVE SAMPLING NETWORK FOR A SWITCHED-CAPACITOR ADC WITH A SLOW REFERENCE GENERATOR
    4.
    发明申请
    LOW NOISE AND LOW POWER PASSIVE SAMPLING NETWORK FOR A SWITCHED-CAPACITOR ADC WITH A SLOW REFERENCE GENERATOR 审中-公开
    具有慢速参考发生器的开关电容ADC的低噪声和低功率无源采样网络

    公开(公告)号：WO2016028650A1

    公开(公告)日：2016-02-25

    申请号：PCT/US2015/045426

    申请日：2015-08-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： ALLADI, Dinesh Jagannath ,  GUO, Yuhua

    IPC: H03M3/02 ,  G06G7/186 ,  H03M3/04

    CPC classification number: G06G7/186 ,  G06G7/1865 ,  H03M3/32 ,  H03M3/342 ,  H03M3/344 ,  H03M3/496 ,  H03M3/50

    Abstract: Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

    Abstract translation: 本公开的某些方面提供用于开关电容器积分器的各种采样网络，其可用于开关电容器模数转换器（ADC）。 不同于输入采样电容器和参考采样电容器两者，本公开的某些方面使用共享采样电容器作为参考电压和输入电压，从而减少ADC输入参考噪声，降低运算放大器面积和功率，以及 避免抗混叠滤波器插入损耗。 此外，通过在采样阶段对参考电压进行采样并使用共享采样电容在积分阶段对输入电压进行采样，高参考电压不需要用于参考电压。

    APPARATUS AND METHOD FOR GENERATING REFERENCE DC VOLTAGE FROM BANDGAP-BASED VOLTAGE ON DATA SIGNAL TRANSMISSION LINE
    7.
    发明申请
    APPARATUS AND METHOD FOR GENERATING REFERENCE DC VOLTAGE FROM BANDGAP-BASED VOLTAGE ON DATA SIGNAL TRANSMISSION LINE 审中-公开

    公开(公告)号：WO2020214310A1

    公开(公告)日：2020-10-22

    申请号：PCT/US2020/023061

    申请日：2020-03-17

    Applicant: QUALCOMM INCORPORATED

    Inventor： SIVAKUMAR, Balasubramanian ,  ALLADI, Dinesh Jagannath ,  YAMAMOTO, Kentaro ,  BAKER, Sean ,  ZHAO, Liang

    IPC: H03K19/0185 ,  H04L25/02 ,  H04B3/00

    Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of Iand Q-data signals, respectively.

    NOISE SHAPING SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
    10.
    发明申请
    NOISE SHAPING SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER 审中-公开
    噪声成像接续逼近寄存器模拟数字转换器

    公开(公告)号：WO2016191054A1

    公开(公告)日：2016-12-01

    申请号：PCT/US2016/030685

    申请日：2016-05-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： RAJAEE, Omid ,  ALLADI, Dinesh Jagannath ,  DAI, Liang

    IPC: H03M3/00

    CPC classification number: H03M3/426 ,  H03M1/466 ,  H03M3/32 ,  H03M3/436

    Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

    Abstract translation: 模数转换器包括：第一输入端，用于接收第一输入信号; 第二输入端子，用于接收第二输入信号; 噪声整形模块，其被配置为将所述第一输入信号与所接收的所述第二输入信号进行比较，并且在噪声整形操作的第一阶段中输出数字输出信号和残留信号; 以及存储模块，被配置为在所述噪声整形操作的第一阶段期间存储所述残留信号，所述存储模块被配置为在所述噪声整形操作的第二阶段中接收模拟输入信号并从所述模拟输入信号中去除所述残留信号， 向噪声整形模块输出新的第一输入信号。

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