公开(公告)号：WO2017053028A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/049396

申请日：2016-08-30

Applicant: QUALCOMM INCORPORATED

Inventor： RAJAEE, Omid ,  DAI, Liang ,  KIRAN, Ganesh

IPC: H03M1/18 ,  H03M1/10 ,  H03M1/38

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

Abstract translation: 本公开的某些方面提供了分段逐次逼近寄存器（SAR）模数转换器（ADC）。 一个示例性ADC通常包括多个SAR ADC电路，每个与ADC的电压范围的不同电压范围段相关联。 每个SAR ADC电路被配置为接收输入到ADC的模拟信号并且基于模拟信号输出数字信号，当模拟信号的电压电平在...之内时，数字信号代表模拟信号的电压电平 与SAR ADC电路相关的分段。 在某些方面，SAR ADC可以包括被配置为基于代表由多个SAR ADC电路中的一个或多个输出的模拟信号的电压电平的一个或多个数字信号来控制ADC的数字输出的逻辑。

公开(公告)号：WO2014022410A1

公开(公告)日：2014-02-06

申请号：PCT/US2013/052748

申请日：2013-07-30

Applicant: QUALCOMM INCORPORATED

Inventor： RAJAEE, Omid ,  DAI, Liang

IPC: H03M3/00

CPC classification number: H03M3/452

Abstract: A low distortion feed forward delta sigma modulator includes a first adder operable to receive a feedback signal and an input signal. The modulator also includes a first integrator operable to receive an output from the first adder, and a second integrator operable to receive an output from the first integrator. The modulator further includes a second adder operable to receive a second integrated path from the second integrator, a first integrating path from the first integrator and a first summing path from the input signal. The modulator also has a last integrator operable to receive an output from the second adder.

Abstract translation: 低失真前馈ΔΣ调制器包括可操作以接收反馈信号和输入信号的第一加法器。 调制器还包括可操作以接收来自第一加法器的输出的第一积分器和可操作以接收来自第一积分器的输出的第二积分器。 调制器还包括第二加法器，可操作以从第二积分器接收第二集成路径，来自第一积分器的第一积分路径和来自输入信号的第一求和路径。 调制器还具有可操作以接收来自第二加法器的输出的最后一个积分器。

公开(公告)号：WO2016191054A1

公开(公告)日：2016-12-01

申请号：PCT/US2016/030685

申请日：2016-05-04

Applicant: QUALCOMM INCORPORATED

Inventor： RAJAEE, Omid ,  ALLADI, Dinesh Jagannath ,  DAI, Liang

IPC: H03M3/00

CPC classification number: H03M3/426 ,  H03M1/466 ,  H03M3/32 ,  H03M3/436

Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

Abstract translation: 模数转换器包括：第一输入端，用于接收第一输入信号; 第二输入端子，用于接收第二输入信号; 噪声整形模块，其被配置为将所述第一输入信号与所接收的所述第二输入信号进行比较，并且在噪声整形操作的第一阶段中输出数字输出信号和残留信号; 以及存储模块，被配置为在所述噪声整形操作的第一阶段期间存储所述残留信号，所述存储模块被配置为在所述噪声整形操作的第二阶段中接收模拟输入信号并从所述模拟输入信号中去除所述残留信号， 向噪声整形模块输出新的第一输入信号。

公开(公告)号：WO2016137647A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/015199

申请日：2016-01-27

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Li ,  ROHAM, Masoud ,  DAI, Liang ,  MERUVA, Anand

IPC: G05F3/22 ,  G01K7/00

CPC classification number: G01K19/00 ,  G01K7/01 ,  G01K7/22 ,  G01K15/005 ,  G05F3/225

Abstract: Systems and methods for sensing temperature on a chip are described herein. In one aspect, a temperature sensing system includes a sensing circuit with matching diode devices for providing corresponding diode voltages proportional to currents through the diode devices. The system also includes a digital code calculation unit for generating a plurality of digital code values based on first and second reference voltages and the diode voltages and a digital calibration engine configured for computing a calibrated temperature based on the plurality of digital codes. The system further includes a switching circuit for routing the diode voltages, during first and second times, to diode voltage input terminals of the digital code calculation unit.

Abstract translation: 本文描述了用于感测芯片上的温度的系统和方法。 在一个方面，温度感测系统包括具有匹配二极管器件的感测电路，用于提供与通过二极管器件的电流成比例的相应的二极管电压。 该系统还包括数字代码计算单元，用于基于第一和第二参考电压和二极管电压产生多个数字代码值，以及数字校准引擎，被配置为基于多个数字代码来计算校准温度。 该系统还包括用于在第一次和第二次期间将二极管电压布置到数字代码计算单元的二极管电压输入端的开关电路。

公开(公告)号：WO2008089460A1

公开(公告)日：2008-07-24

申请号：PCT/US2008/051520

申请日：2008-01-18

Applicant: QUALCOMM Incorporated ,  DAI, Liang ,  LEWIS, Brandon Wayne ,  BRIDGES, Jeffrey Todd ,  CHEN, Weihua

Inventor： DAI, Liang ,  LEWIS, Brandon Wayne ,  BRIDGES, Jeffrey Todd ,  CHEN, Weihua

IPC: H03L7/189

CPC classification number: H03L7/189 ,  H03L2207/06

Abstract: A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.

Abstract translation: 公开了一种采用多个振荡器复合器的锁相环。 锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。 锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

公开(公告)号：WO2016160235A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/020270

申请日：2016-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  DAI, Liang

IPC: H03F1/30 ,  H03F1/32 ,  H03F3/26 ,  H03F1/02

CPC classification number: H03K17/165 ,  H03F1/0233 ,  H03F1/307 ,  H03F1/3217 ,  H03F3/26

Abstract: A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.

Abstract translation: 推挽驱动器设置有差分放大器，其放大输入电压和输出电压之间的差以驱动耦合到二极管连接的偏置晶体管的偏置节点。 推挽驱动器被配置为控制源极跟随器输出晶体管的漏极 - 源极电压，其栅极连接到二极管连接的偏置晶体管的栅极与源极 - 源极电压成比例 二极管连接的偏置晶体管。 这种比例性可以防止在源极跟随器输出晶体管中存在的过大的静态电流变化。

公开(公告)号：WO2016081153A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/057172

申请日：2015-10-23

Applicant: QUALCOMM INCORPORATED

Inventor： ROHAM, Masoud ,  DAI, Liang

IPC: H03F3/347 ,  G05F3/26 ,  G01R19/00 ,  H03F3/50

CPC classification number: G05F3/262 ,  G01R19/0092 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2200/91

Abstract: Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror (200), which includes a first pair of transistors (M4, M5), a second pair of transistors (M2, M3) in cascode with the first pair of transistors (M4, M5), a switching network (201) coupled to the second pair of transistors (M2, M3), and a third pair of transistors (MO, Ml) coupled to the switching network (201). An input node (208) between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node (210) at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low- voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

Abstract translation: 本公开的某些方面通常涉及低电压，精确的电流镜（200），其包括第一对晶体管（M4，M5），第二对晶体管（M2，M3）与第一对晶体管 晶体管（M4，M5），耦合到第二对晶体管（M2，M3）的开关网络（201）和耦合到开关网络（201）的第三对晶体管（MO，M1）。 第一和第二对晶体管之间的输入节点（208）可以被配置为接收电流镜的输入电流，并且第一对晶体管的输出节点（210）可被配置为吸收输出电流 电流镜，与输入电流成正比。 该电流镜架构提供混合低压/高压解决方案，可承受低输入电压，提供高输出阻抗，并提供低面积和功耗。

公开(公告)号：WO2010129824A1

公开(公告)日：2010-11-11

申请号：PCT/US2010/033947

申请日：2010-05-06

Applicant: QUALCOMM Incorporated ,  QUAN, Xiaohong ,  MATHE, Lennart K. ,  DAI, Liang ,  ALLADI, Dinesh J.

Inventor： QUAN, Xiaohong ,  MATHE, Lennart K. ,  DAI, Liang ,  ALLADI, Dinesh J.

IPC: H03K7/08 ,  H03K5/156

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block (210) is provided for computing the product of a selected duty cycle (C) and a discrete ratio (L) between a reference clock period and a high-frequency oscillator period. The computation block (210) may be coupled to a pulse width generator (220) for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period (Tosc). In another aspect, a pulse width generator (220) may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract translation: 用于产生具有可选占空比的周期性数字信号的全数字技术。 在一个方面，提供了一个计算块（210），用于计算一个基准时钟周期和一个高频振荡器周期之间的所选占空比（C）和离散比（L）的乘积。 计算块（210）可以耦合到脉冲宽度发生器（220），用于产生具有作为高频振荡器周期（Tosc）的整数倍的脉冲宽度的信号。 在另一方面，脉冲宽度发生器（220）还可以通过对与高频振荡器周期的环形振荡器示例性实施例的各个逆变器级相匹配的延迟线的各个逆变器级进行接收来适应高频振荡器周期的混合分数倍 振荡器。

公开(公告)号：WO2022191984A2

公开(公告)日：2022-09-15

申请号：PCT/US2022/017218

申请日：2022-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： DAI, Liang ,  YAMAMOTO, Kentaro ,  SEDIGHI, Behnam

IPC: H03K19/096 ,  H03K19/173 ,  H03M1/56 ,  H03K19/0963 ,  H03K19/1733 ,  H03K3/356043 ,  H03M3/436 ,  H03M3/458

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

公开(公告)号：WO2017052921A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048394

申请日：2016-08-24

Applicant: QUALCOMM INCORPORATED

Inventor： RAJAEE, Omid ,  HAN, Changsok ,  DAI, Liang ,  MIRHAJ, Seyed Arash ,  KIRAN, Ganesh

IPC: H03M3/00 ,  H03M1/46 ,  H03M1/10

CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用增加的采样率。