公开(公告)号：WO2016118674A1

公开(公告)日：2016-07-28

申请号：PCT/US2016/014199

申请日：2016-01-21

Applicant: LA GROU, John, Howard

Inventor： LA GROU, John, Howard

IPC: H03M1/66 ,  H03M1/68

CPC classification number: H03M1/08 ,  H03M1/68 ,  H03M1/70

Abstract: A digital-to-analog converter which minimizes noise and optimizes dynamic range by apportioning a least significant bits portion of an incoming digital signal to a low-path circuit and a most significant bits portion of the incoming digital signal to a high-path circuit. The low-path circuit has a low-path digital-to-analog converter, which feeds a low-path amplifier, which feeds a low-path resistive element, which feeds an output node. The high-path circuit has a high-path digital-to-analog converter, which feeds a high-path amplifier, which feeds a high-path resistive element when a high-path switching element is closed, which feeds an output node. The output node is a simple electrical connection of the outputs of the low-path and high-path resistive elements. The high-path switching element is closed when the incoming digital signal has an amplitude above a switching threshold level. Parameters of the circuit, including the sizes of the least significant bits portion and most significant bits portion of the incoming digital signal, are selected such that the switching threshold level is significantly above the noise level produced by the high-path circuit thereby providing psychoacoustic masking of noise produced by the high-path circuit.

Abstract translation: 一种数模转换器，其通过将输入数字信号的最低有效位部分分配给输入数字信号的低通路电路和最高有效位部分到高路径电路来最小化噪声并优化动态范围。 低通路电路具有低通道数模转换器，其馈送低通路放大器，该低通路放大器馈送输入节点的低通路电阻元件。 高路径电路具有高通道数模转换器，其馈送高通路放大器，当高通道开关元件闭合时，高通路放大器馈送高通路电阻元件，馈送输出节点。 输出节点是低通路和高通路电阻元件的输出的简单电连接。 当输入数字信号具有高于开关阈值电平的幅度时，高通道开关元件闭合。 选择电路的参数，包括输入数字信号的最低有效位部分和最高有效位部分的大小，使得开关阈值电平明显高于由高通路电路产生的噪声电平，由此提供心理声学屏蔽 的高通路电路产生的噪声。

公开(公告)号：WO2015168854A1

公开(公告)日：2015-11-12

申请号：PCT/CN2014/076838

申请日：2014-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  ZHANG, Jun ,  ZHANG, Zefei ,  SU, Anzhe ,  MENG, Hao ,  WEN, Xianguang ,  WANG, Xuan

Inventor： ZHANG, Jun ,  ZHANG, Zefei ,  SU, Anzhe ,  MENG, Hao ,  WEN, Xianguang ,  WANG, Xuan

IPC: H03M1/68

CPC classification number: H03M1/68 ,  H03M1/76 ,  H03M1/808

Abstract: Digital to analog converters have first and second to analog arrays. The first digital to analog array has a reference input,a reference output,a first digital input that is connectable to a digital signal,and an analog output. The second digital to analog array includes a reference input, a reference output that is coupled to the reference input of the first digital to analog array,a plurality of switches coupled to the reference input,and a plurality of resistors coupled between the switches and the reference output.

Abstract translation: 数模转换器具有第一和第二到模拟阵列。 第一个数模转换阵列具有参考输入，参考输出，可连接数字信号的第一数字输入和模拟输出。 第二数模转换器阵列包括参考输入，耦合到第一数模转换器阵列的参考输入的参考输出，耦合到参考输入的多个开关，以及耦合在开关和 参考输出。

公开(公告)号：WO2014138336A1

公开(公告)日：2014-09-12

申请号：PCT/US2014/021008

申请日：2014-03-06

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： KUMAR, Ajay

IPC: H03M1/10 ,  H03M1/68 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M1/0617 ,  H03M1/1061 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: A fixed capacitor is coupled between a top plate of an attenuation capacitor and a variable voltage reference. The error in the attenuation capacitor may be calibrated out with the variable voltage reference and the fixed correction capacitor. The variable voltage reference varies the charge on the attenuation capacitor and thereby compensates for error(s) therein. A calibration digital-to-analog converter may be used in conjunction with or substituted for the variable voltage reference, and may be programmed for different charge compensation values from the SAR logic during an iterative SAR DAC capacitive switching process.

Abstract translation: 固定电容器耦合在衰减电容器的顶板和可变电压基准之间。 可以使用可变电压基准和固定校正电容校正衰减电容器的误差。 可变电压基准改变衰减电容器上的电荷，从而补偿其中的误差。 校准数模转换器可以与可变参考电压一起使用或替代，并且可以在迭代SAR DAC电容转换过程期间从SAR逻辑编程用于不同的电荷补偿值。

公开(公告)号：WO2013076273A1

公开(公告)日：2013-05-30

申请号：PCT/EP2012/073523

申请日：2012-11-23

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： BURMEISTER, Dirk ,  CHEMISKY, Eric

IPC: H03M1/68 ,  G05B19/042

CPC classification number: H03M1/68 ,  G05B19/0423 ,  H03M1/822

Abstract: Prozessautomatisierungsgerät mit einer 4-20 mA Stromschnittstelle (3) zum Anschluss an eine Zweidrahtleitung (2) und einem Digital-/Analog-Umsetzer (13), der einen Digitalwert (1) in ein Analogsignal umsetzt und damit die Stromschnittstelle (3) steuert, wobei die Stromschnittstelle (3) einen Stromregler (9) und eine von ihm gesteuerte Transistorschaltung (4) aufweist, die in Reihe mit einem Strommesswiderstand (5) im Stromweg der Zweidrahtleitung (2) liegt, der Digital-/Analog-Umsetzer (13) eine Einrichtung (14) aufweist, die an einem ersten Ausgang (15) einen Grobanteil und an einem zweiten Ausgang (16) einen Feinanteil des Digitalwerts (1) bereitstellt, an dem ersten Ausgang (15) ein erster Pulsweitenmodulator (17) mit nachgeordnetem ersten Tiefpassfilter (18) und erstem Widerstand (19) angeschlossen ist, an dem zweiten Ausgang (16) ein zweiter Pulsweitenmodulator (20) mit nachgeordnetem zweiten Widerstand (21) angeschlossen ist, und der Stromregler (9) als Summierverstärker (8) ausgebildet ist, bei dem an einem eingangsseitigen Summierpunkt (7) der erste und zweite Widerstand (19, 21) und ein an dem Strommesswiderstand (5) angeschlossener dritter Widerstand (6) angeschlossen sind und in dessen Rückkopplungszweig ein zweiter Tiefpassfilter (12) liegt.

Abstract translation: 具有用于连接到双线线路（2）和一个数字/模拟转换器（13），一个数字值（1）转换成模拟信号，并因此电流接口（3）控制一个4-20mA电流环路接口（3）的过程自动化装置， 其中，所述功率接口（3）包括一个电流调节器（9）并通过他控制的晶体管电路（4），其是串联在双线线路（2）的电流路径的电流测量电阻器（5），该数字/模拟转换器（13） 在第一输出（15），一个粗级分和在第二输出端包括装置（14）（16）首先提供的数字值（1）的细级分，在第一输出（15）的第一脉冲宽度调制器（17）与下游 低通滤波器（18）和连接在所述第一电阻器（19）是在所述第二输出端（16）的第二脉冲宽度调制器（20）下游的第二电阻器（21）相连，和电流调节器（9），其为加法放大器（8）AU 在输入侧求和点sgebildet，其中（7）的第一和第二电阻器（19，21）和所述电流测量电阻（5）（6）连接被连接第三电阻和在其反馈支路的第二低通滤波器（12）。

公开(公告)号：WO2007145665A3

公开(公告)日：2008-02-21

申请号：PCT/US2006047045

申请日：2006-12-08

Applicant: ANALOG DEVICES INC ,  HURRELL CHRISTOPHER PETER

Inventor： HURRELL CHRISTOPHER PETER

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/46 ,  H03M1/80

CPC classification number: H03M1/1047 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: An analog to digital converter having improved differential non-linearity is provided. The converter has a memory which is used to look up the actual weight or a weight error corresponding to the bits that have been kept as part of the SAR process to form an output correction value A part of this, for example a residue (the part following the decimal point in a decimal representation) is used to drive a correction DAC which causes a correction to be applied to the trial value presented to a comparator used by the ADC.

Abstract translation: 提供了具有改进的差分非线性的模数转换器。 该转换器具有用于查找与作为SAR处理的一部分保持的比特相对应的实际权重或重量误差的存储器，以形成输出校正值A的一部分，例如残差（部分 遵循十进制表示中的小数点后）用于驱动校正DAC，其导致将校正应用于呈现给ADC使用的比较器的试用值。

公开(公告)号：WO2007145665A2

公开(公告)日：2007-12-21

申请号：PCT/US2006/047045

申请日：2006-12-08

Applicant: ANALOG DEVICES, INC. ,  HURRELL, Christopher, Peter

Inventor： HURRELL, Christopher, Peter

CPC classification number: H03M1/1047 ,  H03M1/468 ,  H03M1/68 ,  H03M1/804

Abstract: An analog to digital converter having improved differential non-linearity is provided. The converter has a memory which is used to look up the actual weight or a weight error corresponding to the bits that have been kept as part of the SAR process to form an output correction value A part of this, for example a residue (the part following the decimal point in a decimal representation) is used to drive a correction DAC which causes a correction to be applied to the trial value presented to a comparator used by the ADC.

Abstract translation: 提供了具有改进的差分非线性的模数转换器。 该转换器具有用于查找与作为SAR处理的一部分保持的比特相对应的实际权重或重量误差的存储器，以形成输出校正值A的一部分，例如残差（部分 遵循十进制表示中的小数点后）用于驱动校正DAC，其导致将校正应用于呈现给ADC使用的比较器的试用值。

公开(公告)号：WO2006068984A9

公开(公告)日：2007-08-02

申请号：PCT/US2005045832

申请日：2005-12-16

Applicant: EXAR CORP ,  FOTOUHI BAHRAM

Inventor： FOTOUHI BAHRAM

IPC: H03M1/78

CPC classification number: H03M1/68 ,  H03M1/76 ,  H03M1/765

Abstract: A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are complementary with respect to a voltage present at the center of the resistor segment disposed in that decoder. A second decoding stage receives the first and second voltages delivered by each of the N decoders and delivers two of these voltages, that are complementary with respect to a voltage present at the center of the resistor, to a pair of third and fourth output nodes.

Abstract translation: 差分数模转换器（VDAC）部分包括电阻器和至少两个解码级。 电阻器被分成N个相等的片段，每个N个等分片段分别设置在形成第一解码级的N个解码器的不同的一个中。 每个解码器中的电阻器段进一步分成M个相等的段以提供M个抽头节点。 第一解码级的每个解码器将两个M抽头电压传送到一对相关联的输出节点，并且相对于存在于设置在该解码器中的电阻器段的中心处的电压互补。 第二解码级接收由N个解码器中的每一个传送的第一和第二电压，并且将相对于存在于电阻器中心的电压互补的这些电压中的两个输出到一对第三和第四输出节点。

公开(公告)号：WO01056062A2

公开(公告)日：2001-08-02

申请号：PCT/US2001/002391

申请日：2001-01-24

IPC: G05G9/047 ,  G06F1/32 ,  G06F3/038 ,  H02J7/00 ,  H03K3/012 ,  H03L3/00 ,  H03M1/68 ,  H03M1/82 ,  H01L

CPC classification number: G06F3/0383 ,  G05G9/047 ,  G05G2009/04777 ,  G06F1/3203 ,  G06F1/3237 ,  H03K3/012 ,  H03L3/00 ,  H03M1/68 ,  H03M1/82 ,  Y02D10/128

Abstract: The problem of battery failure due to failure of one cell in a rechargeable battery, and the related problem of inefficient use of a battery over its dynamic range due to differences between the performance of cells in a battery, are addressed by providing one or more capacitors selectively coupled to the various cells of the battery. The selective and repetitive coupling of capacitors to the cells permits balancing of charge among the cells. This minimizes the risk that any one cell would suffer catastrophic failure due to being fully charged or discharged prior to the other cells in the battery. This also permits making use of the battery over nearly all of its dynamic range. In this way, battery life is maximized.

Abstract translation: 由于可再充电电池中的一个电池的故障导致的电池故障的问题以及由于电池中的电池的性能之间的差异而在其动态范围内低效使用电池的相关问题通过提供一个或多个电容器 选择性地耦合到电池的各个单元。 电容器与电池的选择性和重复耦合允许电池间的电荷平衡。 这使得任何一个电池由于在电池中的其它电池之前被完全充电或放电而遭受灾难性故障的风险最小化。 这也允许在几乎所有动态范围内使用电池。 以这种方式，电池寿命最大化。

公开(公告)号：WO98048515A1

公开(公告)日：1998-10-29

申请号：PCT/US1998/007827

申请日：1998-04-16

IPC: H03M1/08 ,  H03M3/02 ,  H03M3/04 ,  H03M3/00

CPC classification number: H03M1/067 ,  H03M1/68 ,  H03M1/74 ,  H03M3/502

Abstract: An error-shaping digital-to-analog (D/A) converter system (100), consisting of a separator (102), a set of D/A converters (104, 108), a set of optional analog filters (106, 108), a summation device (112), and an optional analog filter (114). The separator (102) separates the digital input signal into a set of low-resolution signals of which only one has significant power in the system's signal band. These signals are D/A converted by mismatch-shaping D/A converters (104, 108), in some embodiments filtered by analog filters (106, 108), and then added by the summing device (112). Imperfections of the employed D/A converters (104, 108) will only cause very small errors in the signal band, such errors being essentially uncorrelated to the digital input signal. The D/A converter system is comparable to a scaled-element D/A converter in which the distortion is transformed into a noise component having very little power in the signal band.

Abstract translation: 一种由分离器（102），一组D / A转换器（104,108），一组可选的模拟滤波器（106,108）组成的数字模拟（D / A）转换器系统（100） 108），求和装置（112）和可选的模拟滤波器（114）。 分离器（102）将数字输入信号分离成一组低分辨率信号，其中仅一个在系统的信号频带中具有有效功率。 这些信号是由失配整形D / A转换器（104,108）转换的D / A，在一些实施例中由模拟滤波器（106,108）滤波，然后由求和装置（112）加法。 使用的D / A转换器（104,108）的缺陷将仅在信号频带中产生非常小的误差，这样的误差基本上与数字输入信号不相关。 D / A转换器系统与其中失真被转换成在信号频带中具有非常小的功率的噪声分量的缩放元件D / A转换器相当。

公开(公告)号：WO1992001336A1

公开(公告)日：1992-01-23

申请号：PCT/US1991004551

申请日：1991-07-02

Applicant: DAVID SARNOFF RESEARCH CENTER, INC.

Inventor： DAVID SARNOFF RESEARCH CENTER, INC. ,  SAUER, Donald, Jon

IPC: H03M01/38

CPC classification number: H03M1/1023 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/1033 ,  H03M1/1215 ,  H03M1/46 ,  H03M1/68

Abstract: There is disclosed an ADC (18) including a comparator (40) which sets, bit-by-bit, a successive approximation binary register (42). Feedback means (42, 44, 48) for auto-biasing, auto calibration, and offset compensation within the ADC (18) are provided. The ADC (18) sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs (18) are connected in parallel to provide an increased sampling rate. The ADC (18) architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC (18) operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.