公开(公告)号：WO2021112978A1

公开(公告)日：2021-06-10

申请号：PCT/US2020/057826

申请日：2020-10-29

Applicant: QUALCOMM INCORPORATED

Inventor： ZHANG, Chaoqi ,  KUMAR, Rajneesh ,  WENG, Li-Sheng ,  JESSIE, Darryl Sheldon ,  HWANG, Suhyung ,  HAN, Jeahyeong ,  CHEN, Xiaoming ,  YEON, Jaehyun

IPC: H01L23/498 ,  H01L23/552 ,  H01L21/56 ,  H01L23/31 ,  H05K1/02

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

公开(公告)号：WO2022256117A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/027875

申请日：2022-05-05

Applicant: QUALCOMM INCORPORATED

Inventor： WENG, Li-Sheng ,  PAYNTER, Charles David ,  LANE, Ryan ,  XU, Jianwen ,  STONE, William

IPC: H01L21/60 ,  H01L25/065 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/08225 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/214 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73251 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L24/02 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2924/15192

Abstract: A package (200) comprising a first integrated device (202) comprising a plurality of first pillar interconnects /227); an encapsulation layer (206) at least partially encapsulating the first integrated-device; a metallization portion (211) located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer (210/212) and a plurality of metallization layer interconnects (203), wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device (204) comprising a plurality of second pillar interconnects (247), wherein the second integrated device is coupled to the plurality of metallization layer interconnects (203) through a plurality of second pillar interconnects and a plurality of solder interconnects (230).

公开(公告)号：WO2022203810A1

公开(公告)日：2022-09-29

申请号：PCT/US2022/017904

申请日：2022-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  ZHOU, Rong ,  WENG, Li-Sheng ,  ZHAO, Lily

IPC: H01L23/13

Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

公开(公告)号：WO2022133372A1

公开(公告)日：2022-06-23

申请号：PCT/US2021/072111

申请日：2021-10-29

Applicant: QUALCOMM INCORPORATED

Inventor： WENG, Li-Sheng ,  CHEN, Yu-Chih ,  ZHANG, Chaoqi

IPC: H01L23/552 ,  H01L21/60

Abstract: Fan-out wafer-level packaging (FOWLP) integrated circuits (ICs) employing electro-magnetic (EM) interference (EMI) shield structure in fan out area for EMI shielding, and related fabricating methods are disclosed. The IC includes a semiconductor die (" IC die") (402) that is bonded to the reconstituted carrier wafer such that a fan-out area (404) is provided between adjacent IC dies to provide area for fan¬ out interconnects to provide additional die interconnections to the IC die. In exemplary aspects, the IC includes an EMI shield (408) that includes vias (406) formed in an un-used area in fan-out area adjacent to the IC die electrically that are otherwise unused for input/output (I/O) signal interconnects (434) for coupling I/O signals to the IC die. The EMI shield is electrically coupled to a ground node (410) of the IC die to provide an effectively shield to block or attenuate unwanted EM noise propagated from the IC die to the outside.

公开(公告)号：WO2022232746A1

公开(公告)日：2022-11-03

申请号：PCT/US2022/071738

申请日：2022-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： WENG, Li-Sheng ,  WE, Hong Bok

IPC: H01L21/60 ,  H01L21/683 ,  H01L21/56

Abstract: Disclosed is an apparatus including a molded multi-die high density interconnect including: a bridge die (140) having a first plurality of interconnects (141) and second plurality of interconnects (142). The apparatus also includes a first die (110) having a first plurality of contacts (112) and a second plurality of contacts (114), where the second plurality of contacts is coupled to the first plurality of interconnects of the bridge die. The apparatus also includes a second die (120) having a first plurality of contacts (122) and a second plurality of contacts (124), where the second plurality of contacts is coupled to the second plurality of interconnects of the bridge die. The coupled second plurality of contacts and interconnects have a smaller height than the first plurality of contacts of the first die and second die.

公开(公告)号：WO2022103531A1

公开(公告)日：2022-05-19

申请号：PCT/US2021/054044

申请日：2021-10-07

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  WENG, Li-Sheng ,  SONG, Zhimin

IPC: H01L25/065 ,  H01L23/12 ,  H01L21/60 ,  H01L21/98 ,  H01L21/56 ,  H01L25/16 ,  H01L25/18

Abstract: A package comprising a substrate (202), a first integrated device (204) coupled to the substrate, a second integrated device (206) coupled to the substrate, an interconnect integrated device (201) coupled to the first integrated device and the second integrated device, and an underfill. The substrate includes a cavity (209). The interconnect integrated device is located over the cavity of the substrate. The underfill (208) is located (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.

公开(公告)号：WO2021194857A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023035

申请日：2021-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： LANE, Ryan ,  WENG, Li-Sheng ,  PAYNTER, Charles David ,  FORONDA, Eric David

IPC: H01L25/065 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

公开(公告)号：WO2021086491A1

公开(公告)日：2021-05-06

申请号：PCT/US2020/048875

申请日：2020-09-01

Applicant: QUALCOMM INCORPORATED

Inventor： WENG, Li-Sheng ,  LI, Yue ,  SUN, Yangyang

IPC: H01L21/48 ,  H01L23/498

Abstract: An integrated device that includes a substrate, an interconnect portion and an interconnect structure. The interconnect portion is located over the substrate. The interconnect portion includes a plurality of interconnects and at least one dielectric layer. The interconnect structure is located over the interconnect portion. The interconnect structure includes an inner interconnect, a dielectric layer coupled to the inner interconnect, and an outer conductive layer coupled to the dielectric layer. The outer conductive layer is configured to operate as a shield for the inner interconnect.