公开(公告)号：WO2022203810A1

公开(公告)日：2022-09-29

申请号：PCT/US2022/017904

申请日：2022-02-25

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  ZHOU, Rong ,  WENG, Li-Sheng ,  ZHAO, Lily

IPC: H01L23/13

Abstract: A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

公开(公告)号：WO2014070926A1

公开(公告)日：2014-05-08

申请号：PCT/US2013/067568

申请日：2013-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  ZHAO, Lily ,  HAN, Michael

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L29/43 ,  B81B2207/093 ,  B81C1/00269 ,  B81C2203/019 ,  H01L21/768 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L29/84 ,  H01L2224/02166 ,  H01L2224/03019 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/10126 ,  H01L2224/11019 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/1183 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13138 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13163 ,  H01L2224/13565 ,  H01L2224/13687 ,  H01L2224/13688 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/05442 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01034 ,  H01L2924/0109 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A conductive interconnect (340, 440, 540, 640) includes a conductive support layer (330, 430, 530, 630), a conductive material (320, 520, 620) on the conductive support layer (330, 430, 530, 630) and an inorganic collar (350, 450, 550, 650) partially surrounding the conductive material (320, 520, 620). The inorganic collar (350, 450, 550, 650) is also disposed on sidewalls of the conductive support layer (330, 430, 530, 630). A method of fabricating the conductive interconnect (340, 440, 540, 640) comprises fabricating a conductive material (320, 520, 620) on a seed layer (304, 504), forming an organic collar (310, 510) to partially surround the conductive material (320, 520, 620), etching the conductive seed layer (304, 504) to form the conductive support layer (330, 430, 530, 630) and heating to transition the organic collar (310, 510) into the inorganic collar (350, 450, 550, 650) that partially surrounds the conductive material (320, 520, 620) and is disposed on sidewalls of the conductive support layer (330, 430, 530, 630). The organic collar (310, 510) may be formed by depositing a photosensitive spin on dielectric material on the conductive material (320, 520, 620) and patterning the photosensitive spin on dielectric material. The conductive material (620) may be a single conductive material (320) or may comprise a stack of a first conductive layer (322) and a second conductive layer (324), separated by a barrier layer, in which case the heating step also causes a reflow of the second conductive layer (324) of the conductive material stack.

Abstract translation: 导电互连（340,440,540,640）包括导电支撑层（330,430,530,630），导电支撑层（330,430,530,630）上的导电材料（320,520,620） ）和部分地围绕导电材料（320,520,620）的无机套环（350,450,550,650）。 无机套环（350,450,550,650）也设置在导电支撑层（330,430,530,630）的侧壁上。 制造导电互连（340,440,540,640）的方法包括在种子层（304,504）上制造导电材料（320,520,620），形成有机套环（310,510）以部分地包围 所述导电材料（320,520,620）蚀刻所述导电种子层（304,504）以形成所述导电支撑层（330,430,530,630）并加热以将所述有机套环（310,510）转变成所述导电材料层 部分地围绕导电材料（320,520,620）并且设置在导电支撑层（330,430,530,630）的侧壁上的无机套环（350,450,550,650）。 可以通过在导电材料（320,520,620）上沉积介电材料上的光敏自旋并使电介质材料上的感光纺丝图案来形成有机套环（310,510）。 导电材料（620）可以是单个导电材料（320），或者可以包括由阻挡层隔开的第一导电层（322）和第二导电层（324）的堆叠，在这种情况下，加热步骤也 导致导电材料堆叠的第二导电层（324）的回流。

公开(公告)号：WO2022182461A2

公开(公告)日：2022-09-01

申请号：PCT/US2022/013697

申请日：2022-01-25

Applicant: QUALCOMM INCORPORATED

Inventor： HU, Wei ,  HE, Dongming ,  YIN, Wen ,  GUAN, Zhe ,  ZHAO, Lily

IPC: H01L23/485 ,  H01L21/60 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11622 ,  H01L2224/118 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13171 ,  H01L2224/13565 ,  H01L2224/13584 ,  H01L2224/13624 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13686 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/3651 ,  H01L2924/381 ,  H01L2924/3841

Abstract: An IC package (900A-E) includes a substrate (920) and an integrated circuit (IC) structure comprising a die (410, 510, 610, 710, 810) (e.g., a flip-chip (FC) die) and one or more die interconnects (430) to electrically couple the die (410, 510, 610, 710, 810) to the substrate (920). The die interconnect (430) includes a pillar (440, 540, 640, 740, 840), a wetting barrier (460, 560, 660, 760, 860) on the pillar (440, 540, 640, 740, 840), and a solder cap (450, 550, 650, 750, 850) on the wetting barrier (460, 560, 660, 760, 860). The wetting barrier (460, 560, 660, 760, 860) is wider than the pillar (440, 540, 640, 740, 840), such that, during solder reflow, solder wetting of sidewall of the pillar (440, 540, 640, 740, 840) is minimised or prevented altogether. The width of the wetting barrier (460, 560, 660, 760, 860) may be greater than a width of the solder cap (450, 550, 650, 750, 850). The die interconnect (430) may also include a low wetting layer (470, 570, 770, 870) formed on at least a portion of a surface of the wetting barrier (460, 560, 760, 860) not covered by the pillar (440, 540, 740, 840), which can further mitigate solder wetting problems. The low wetting layer (470, 570, 770, 870) may have a lower solderability than the pillar (440, 540, 740, 840), for example, it may be made from metals such as Ni, Al, Cr, etc. The pillar (440, 540, 740) and the wetting barrier (460, 560, 760) may be formed from a same conductive material (e.g., Cu). Alternatively, the pillar (440) and the wetting barrier (460) may be formed from different conductive materials, with the material of the wetting barrier (460) (e.g., Ni) selected so as to also provide a chemical barrier to solder wetting on sidewalls of the pillar (440) (e.g., Cu). The IC structure may further comprise a contact layer (e.g., Ni) (780) in between the wetting barrier (760) and the solder cap (750). Alternatively, the low wetting layer (570, 870) may also be formed in between the wetting barrier (560, 860) and the solder cap (550, 850), wherein the pillar (840) may further be a first pillar, the IC structure further comprising a second pillar (890) (e.g., Cu) on the low wetting layer (870) and a contact layer (e.g., Ni) (880) between the second pillar (890) and the solder cap (850).

公开(公告)号：WO2022005669A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/034862

申请日：2021-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Yangyang ,  HE, Dongming ,  ZHAO, Lily

IPC: H01L23/00 ,  H01L23/498 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05147 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06163 ,  H01L2224/06164 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13211 ,  H01L2224/13239 ,  H01L2224/1403 ,  H01L2224/14164 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2924/014

Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

公开(公告)号：WO2018208524A1

公开(公告)日：2018-11-15

申请号：PCT/US2018/030168

申请日：2018-04-30

Applicant: QUALCOMM INCORPORATED

Inventor： HE, Dongming ,  ZHAO, Lily ,  WANG, Wei ,  SYED, Ahmer

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/0221 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03466 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/0544 ,  H01L2924/00012 ,  H01L2924/07025 ,  H01L2924/01028 ,  H01L2924/05042 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A device comprising a semiconductor die and a redistribution portion coupled to the semiconductor die. The redistribution portion includes a passivation layer and a redistribution interconnect comprising a first surface and a second surface opposite to the first surface. The redistribution interconnect is formed over the passivation layer such that the first surface is over the passivation layer and the second surface is free of contact with any passivation layer. The device includes a bump interconnect coupled to the second surface of the redistribution interconnect. In some implementations, the bump interconnect comprises a surface that faces the redistribution interconnect, and wherein an entire surface of the bump interconnect that faces the redistribution interconnect is free of contact with the passivation layer.

公开(公告)号：WO2014011612A2

公开(公告)日：2014-01-16

申请号：PCT/US2013/049682

申请日：2013-07-09

Applicant: QUALCOMM INCORPORATED

Inventor： BAO, Zhongping ,  ZHAO, Lily ,  HAN, Michael

IPC: H01L23/485

CPC classification number: H01L24/14 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/06051 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06141 ,  H01L2224/06145 ,  H01L2224/06517 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/14145 ,  H01L2224/811 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: Some exemplary embodiments of this disclosure pertain to a semiconductor package that includes a packaging substrate, a die and a set of under bump metallization (UBM) structures coupled to the packaging substrate and the die. Each UBM structure has a non-circular cross-section along its respective lateral dimension. Each UBM structure includes a first narrower portion and a second wider portion. The first narrower portion has a first width. The second wider portion has a second width that is greater than the first width. Each UBM structure is oriented towards a particular region of the die such that the first narrower portion of the UBM structure is closer than the second wider portion of the UBM structure to the particular region of the die.

Abstract translation: 本公开的一些示例性实施例涉及一种半导体封装，其包括封装衬底，管芯和耦合到封装衬底和管芯的一组凸底下金属化（UBM）结构。 每个UBM结构沿其各自的横向尺寸具有非圆形横截面。 每个UBM结构包括第一较窄部分和第二较宽部分。 第一较窄部分具有第一宽度。 第二较宽部分具有大于第一宽度的第二宽度。 每个UBM结构朝向管芯的特定区域定向，使得UBM结构的第一较窄部分比UBM结构的第二较宽部分更靠近管芯的特定区域。

公开(公告)号：WO2010141624A2

公开(公告)日：2010-12-09

申请号：PCT/US2010/037120

申请日：2010-06-02

Applicant: QUALCOMM Incorporated ,  BCHIR, Omar, J. ,  ZHAO, Lily

Inventor： BCHIR, Omar, J. ,  ZHAO, Lily

IPC: H01L23/00

CPC classification number: H01L24/12 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11822 ,  H01L2224/11831 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81193 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A pillar for flip chip interconnect in an electronic package. The pillar includes an electrically conductive material and a solder wicking inhibitor deposited on the sides of the pillar. The pillar also includes an exposed face for contacting the electrically conductive material and solder material on the substrate. In another embodiment, a method of forming a pillar composed of an electrically conductive material which inhibits solder wicking is provided. The method includes coating the pillar with a solder wicking inhibitor and polishing a face of the pillar to expose the underlying electrically conductive material.

Abstract translation: 一种用于电子封装中倒装芯片互连的支柱。 支柱包括沉积在柱的侧面上的导电材料和焊料芯吸抑制剂。 该柱还包括用于使导电材料和衬底上的焊料材料接触的暴露面。 在另一个实施例中，提供了形成由阻止焊料芯吸的导电材料构成的柱的方法。 该方法包括用焊料芯吸抑制剂涂覆柱，并抛光柱的表面以暴露下面的导电材料。