公开(公告)号：WO2022002464A1

公开(公告)日：2022-01-06

申请号：PCT/EP2021/061669

申请日：2021-05-04

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： SCHMENGER, Jens ,  KÖGLER, Roman ,  LUFT, Alexander ,  NAMYSLO, Lutz ,  ROPPELT, Bernd ,  SCHWINN, Thomas

IPC分类号： H01L23/467 ,  H01L23/373 ,  H01L25/07 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L21/4882 ,  H01L2224/06181 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32227 ,  H01L2224/40227 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8384 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L25/072 ,  H01L25/115 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/19107

摘要： Die Erfindung betrifft ein Leistungsmodul (2) mit mindestens zwei Leistungseinheiten (4), welche jeweils mindestens einen Leistungshalbleiter (6) und ein Substrat (8) umfassen. Um den erforderlichen Bauraum des Leistungsmoduls zu verringern und eine Entwärmung zu verbessern, wird vorgeschlagen, dass der jeweils mindestens eine Leistungshalbleiter (6), insbesondere stoffschlüssig, mit dem jeweiligen Substrat (8) verbunden ist, wobei die Substrate (8) der mindestens zwei Leistungseinheiten (4) jeweils unmittelbar stoffschlüssig mit einer Oberfläche (24) eines gemeinsamen Kühlkörpers (26) verbunden sind.

公开(公告)号：WO2021262368A1

公开(公告)日：2021-12-30

申请号：PCT/US2021/033915

申请日：2021-05-24

申请人： QUALCOMM INCORPORATED

发明人： WE, Hong Bok ,  HSU, Marcus ,  PATIL, Aniket

IPC分类号： H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73251 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80203 ,  H01L2224/80896 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/83192 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/562 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/50 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511

摘要： Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

公开(公告)号：WO2022038062A2

公开(公告)日：2022-02-24

申请号：PCT/EP2021/072656

申请日：2021-08-13

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM DEUTSCHLAND GMBH

发明人： ABRAHAM, David ,  COTTE, John ,  HALL, Shawn

IPC分类号： H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  G06N10/00 ,  H01L39/02 ,  H01L23/13 ,  H01L23/36 ,  H01L27/18 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2924/15153 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L39/025 ,  H05K1/0216 ,  H05K1/0237

摘要： A method for forming an electronic chip assembly. A first metal plate is coupled to a first side of a substrate to form a backing plate. A first cavity is created extending through the substrate to extend at least to the first metal plate. An electronic component is bonded to the substrate such that the electronic component is located within the first cavity. A second metal plate, having a second cavity, is disposed to a second side of the substrate, and over the first cavity such that the electronic component is encased within the first and second cavities by the first and second metal plates.

公开(公告)号：WO2021243225A8

公开(公告)日：2021-12-02

申请号：PCT/US2021/034882

申请日：2021-05-28

申请人： FORMFACTOR, INC.

发明人： HENSON, Roy J. ,  POWELL, Shawn O.

IPC分类号： H01L21/04 ,  H01L21/48 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L29/66 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01R12/523 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/09063 ,  H05K2201/10303 ,  H05K2201/1034 ,  H05K2201/10378 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/1059 ,  H05K2201/10606 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/041 ,  H05K3/325 ,  H05K3/3405 ,  H05K3/366 ,  H05K3/368

摘要： 3D electrical integration is provided by connecting several component carriers to a single substrate using contacts at the edges of the component carriers making contact to a 2D contact array (e.g., a ball grid array or the like) on the substrate. The resulting integration of components on the component carriers is 3D, thereby providing much higher integration density than in 2D approaches.

公开(公告)号：WO2021194857A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023035

申请日：2021-03-18

申请人： QUALCOMM INCORPORATED

发明人： LANE, Ryan ,  WENG, Li-Sheng ,  PAYNTER, Charles David ,  FORONDA, Eric David

IPC分类号： H01L25/065 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A package comprising a substrate, an integrated device, and an interconnect integrated device. The substrate includes a first surface and a second surface. The substrate further includes a plurality of interconnects. The integrated device is coupled to the substrate. The interconnect integrated device is coupled to a surface of the substrate. The integrated device, the interconnect integrated device and the substrate are configured to provide an electrical path for an electrical signal of the integrated device, that travels through at least the substrate, then through the interconnect integrated device and back through the substrate.

公开(公告)号：WO2022238131A2

公开(公告)日：2022-11-17

申请号：PCT/EP2022/061329

申请日：2022-04-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

发明人： SIKKA, Kamal ,  COURNOYER, Maryse ,  GAGNON, Pascale ,  BUREAU, Charles ,  DUFORT, Catherine ,  MCHERRON, Dale Curtis ,  KHANNA, Vijayeshwar Das ,  BERGENDAHL, Marc ,  PAREKH, Dishit Paresh ,  BONAM, Ravi ,  MORI, Hiroyuki ,  LIU, Yang ,  ANDRY, Paul ,  DE SOUSA, Isabel

IPC分类号： H01L21/60 ,  H01L25/065 ,  H01L21/98 ,  H01L23/16 ,  H01L23/13 ,  H01L21/4853 ,  H01L21/4867 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16257 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17505 ,  H01L2224/27312 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/29078 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81019 ,  H01L2224/81065 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81855 ,  H01L2224/81903 ,  H01L2224/81907 ,  H01L2224/81986 ,  H01L2224/83065 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L23/3675 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/1616 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/3512

摘要： A direct bonded heterogeneous integration (DBHi) device includes a substrate (224) including a trench (220) formed in a top surface of the substrate. The DBHi device further includes a first chip (208) coupled to the substrate on a first side of the trench by a plurality of first interconnects (256). The DBHi device further includes a second chip (212) coupled to the substrate on a second side of the trench by a plurality of second interconnects (256). The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge (204) coupled to the first chip and to the second chip by a plurality of third interconnects (216) such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material (218) surrounding the plurality of third interconnects (216) to further couple the bridge to the first chip and to the second chip.

公开(公告)号：WO2021194858A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023038

申请日：2021-03-18

申请人： QUALCOMM INCORPORATED

发明人： PAYNTER, Charles David ,  LANE, Ryan ,  EATON, John ,  MANO, Amit

IPC分类号： H01L23/552 ,  H01L25/065 ,  H01L23/538 ,  H01L21/683 ,  H01L25/00 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68386 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/95 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0213 ,  H05K1/119 ,  H05K3/30 ,  H05K5/0017 ,  H05K9/0022

摘要： A device that includes a board, a package and a patch substrate. The board includes a cavity. The package is coupled to a first side of the board. The package includes a substrate and an integrated device coupled to the substrate. The integrated device is located at least partially in the cavity of the board. The patch substrate is coupled to a second side of the board. The patch substrate is located over the cavity of the board. The patch substrate is configured as an electromagnetic interference (EMI) shield for the package.

公开(公告)号：WO2015069184A1

公开(公告)日：2015-05-14

申请号：PCT/SG2014/000470

申请日：2014-10-07

申请人： THALES SOLUTIONS ASIA PTE LTD. ,  CNRS - CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (EPST) ,  NANYANG TECHNOLOGICAL UNIVERSITY

发明人： TAN, Dunlin ,  YU, Jong Jen ,  HEE, David ,  TAY, Beng Kang ,  BAILLARGEAT, Dominique

IPC分类号： H01L23/552 ,  H01L23/04 ,  H01L23/498 ,  H01L23/66 ,  H01L25/065 ,  H01L25/16 ,  H05K9/00 ,  B82Y10/00 ,  H01L2223/6616 ,  H01L2223/6683 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32165 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49877 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L29/0676 ,  H01L29/413 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/157 ,  H01L2924/3025 ,  H05K9/0022

摘要： A method of fabricating an electrical guard structure for providing signal isolation is provided. The method includes providing a substrate having a mounting surface comprising a first area for hosting at least one electronic component. The method further comprises synthesizing a plurality of thread-like structures over the substrate to collectively form one or more electrically conductive projections extending transverse to the mounting surface. The one or more electrically conductive projections include one or more wall-like structures which are elongate parallel to the mounting surface. The electrically conductive projections can be transferred to another surface such as a major surface of a second substrate. There are further provided a support structure and a guard structure having the wall-like electrically conductive projections which are electrically grounded when in use to provide signal isolation.

公开(公告)号：WO2022271376A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/030533

申请日：2022-05-23

申请人： QUALCOMM INCORPORATED

发明人： CHAVA, Bharani ,  ROY, Abinash ,  SONG, Stanley Seungchul ,  KIM, Jonghae

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50

摘要： A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, a first bridge and a second bridge. The first bridge is coupled to the first integrated device and the second integrated device. The first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device. The first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device. The second bridge is coupled to the first integrated device and the second integrated device. The second bridge is configured to provide at least one second electrical path between the first integrated device and the second integrated device.

公开(公告)号：WO2021252100A1

公开(公告)日：2021-12-16

申请号：PCT/US2021/030697

申请日：2021-05-04

申请人： QUALCOMM INCORPORATED

发明人： LAN, Je-Hsiung ,  KIM, Jonghae ,  DUTTA, Ranadeep

IPC分类号： H01L23/522 ,  H01F17/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L21/4882 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L23/3128 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/1421

摘要： A semiconductor package is described. The semiconductor package includes a passive substrate and a first integrated passive device (IPD) in a first interlayer-dielectric (ILD) layer on the passive substrate. The semiconductor package also includes a second ILD layer on the first ILD layer. The semiconductor package further includes a second IPD in a third ILD layer on the second ILD layer. The semiconductor package also includes a thermal mitigation structure on inductive elements of the second IPD.