PARTITIONED GAME CONSOLE SYSTEM
    1.
    发明申请
    PARTITIONED GAME CONSOLE SYSTEM 审中-公开
    分区式游戏控制台系统

    公开(公告)号:WO2008014189A3

    公开(公告)日:2008-03-20

    申请号:PCT/US2007073964

    申请日:2007-07-20

    Abstract: The game console system includes a user interface module and a graphics processing module that are remotely situated from one another and solely coupled to one another via one or more communication links. The graphics processing module is positioned within a controlled environment chamber that thermally and acoustically isolates the user interface module from the graphics processing module. The user interface module includes a controller and a console coupled to the controller. The console also is configured to be coupled to a display.

    Abstract translation: 游戏控制台系统包括用户接口模块和图形处理模块,其经由一个或多个通信链路彼此远程位置并且彼此独立地耦合。 图形处理模块位于受控的环境室内,其热和声学地将用户界面模块与图形处理模块隔离。 用户接口模块包括控制器和耦合到控制器的控制台。 控制台还被配置为耦合到显示器。

    AN APPARATUS AND METHOD FOR THERMAL REGULATION IN MEMORY SUBSYSTEMS
    5.
    发明申请
    AN APPARATUS AND METHOD FOR THERMAL REGULATION IN MEMORY SUBSYSTEMS 审中-公开
    一种用于存储子系统中的热调节的装置和方法

    公开(公告)号:WO0004481A3

    公开(公告)日:2000-03-30

    申请号:PCT/US9916063

    申请日:1999-07-16

    Applicant: RAMBUS INC

    Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory device coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature of the memory device. Based on the operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

    Abstract translation: 公开了配置成提供多个存储器设备的热调节的存储器系统。 存储器系统包括耦合到总线的存储器设备。 另外,存储器系统还包括耦合到总线的控制器。 控制器确定存储器装置的操作温度。 基于存储器装置的操作温度,控制器进一步可操作以操纵存储器系统的操作。

    APPARATUS AND METHOD FOR PIPELINED MEMORY OPERATIONS
    6.
    发明申请
    APPARATUS AND METHOD FOR PIPELINED MEMORY OPERATIONS 审中-公开
    用于流水线存储器操作的装置和方法

    公开(公告)号:WO9919875A3

    公开(公告)日:1999-09-02

    申请号:PCT/US9821458

    申请日:1998-09-09

    Applicant: RAMBUS INC

    Abstract: A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

    Abstract translation: 存储器设备具有构成流水线级的接口电路和存储器核,每个级都是与存储器核相关的通用序列中的一个步骤。 存储器件具有处理与操作单元耦合的存储器核心的原语操作的多个操作单元,例如预充电,读出,读取和写入。 所述存储装置还包括多个传输单元,所述多个传输单元被配置为从外部连接获得指定所述操作单元之一的操作的信息并且在所述存储器核心和所述外部连接之间传输数据。 传输单元与操作单元并行地作为流水线的附加阶段操作,由此创建在普通应用的存储器参考流下以高吞吐量和低服务时间操作的存储器设备。

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