公开(公告)号：WO2014016678A3

公开(公告)日：2014-05-15

申请号：PCT/IB2013001878

申请日：2013-06-20

Applicant: MAGNACOM LTD ,  ELIAZ AMIR

Inventor： ELIAZ AMIR

IPC: H04L27/06

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04B1/0475 ,  H04B1/10 ,  H04B1/16 ,  H04B1/709 ,  H04B17/0085 ,  H04B17/15 ,  H04B17/29 ,  H04B2001/0416 ,  H04L1/0036 ,  H04L1/0048 ,  H04L1/005 ,  H04L1/0054 ,  H04L1/203 ,  H04L1/206 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/02 ,  H04L7/042 ,  H04L23/02 ,  H04L25/0236 ,  H04L25/03006 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03178 ,  H04L25/03197 ,  H04L25/03267 ,  H04L25/0328 ,  H04L25/03305 ,  H04L25/03318 ,  H04L25/03337 ,  H04L25/03343 ,  H04L25/03834 ,  H04L25/03885 ,  H04L25/03949 ,  H04L25/08 ,  H04L27/00 ,  H04L27/01 ,  H04L27/02 ,  H04L27/04 ,  H04L27/2278 ,  H04L27/36 ,  H04L27/366 ,  H04L27/368 ,  H04L27/38 ,  H04L2025/03369

Abstract: A receiver may be operable to generate estimates of transmitted symbols using a sequence estimation process that may incorporate a non-linear model. The non-linear model may be adapted by the receiver based on particular communication information that may be indicative of non-linearity experienced by the transmitted symbols. The receiver may generate a reconstructed signal from the estimates of the transmitted symbols. The receiver may adapt the non-linear model based on values of an error signal generated from the reconstructed signal, and the values of the error signal may be generated from a portion of the generated estimates that may correspond to known symbols and/or information symbols. The values of the error signal corresponding to the known symbols may be given more weight in an adaptation algorithm, and the values of the error signal corresponding to the information symbols may be given less weight in the adaptation algorithm.

Abstract translation: 接收机可以可操作以使用可以包含非线性模型的序列估计过程来生成发送符号的估计。 非线性模型可以由接收机根据特定的通信信息进行调整，该通信信息可以指示被发送符号经历的非线性。 接收机可以从所发送的符号的估计中产生重建的信号。 接收机可以基于从重构信号生成的误差信号的值来适配非线性模型，并且可以从可能对应于已知符号和/或信息符号的所产生的估计的一部分生成误差信号的值 。 可以在自适应算法中给出对应于已知符号的误差信号的值，并且在自适应算法中可以给予对应于信息符号的误差信号的权重更小的权重。

公开(公告)号：WO2004093144A2

公开(公告)日：2004-10-28

申请号：PCT/US2004/010980

申请日：2004-04-09

Applicant: RAMBUS, INC. ,  STOJANOVIC, Vladimir, M. ,  HOROWITZ, Mark, A. ,  ZERBE, Jared, L. ,  BESSIOS, Anthony ,  HO, Andrew, C., C. ,  WEI, Jason, C. ,  TSANG, Grace ,  GARLEPP, Bruno, W.

Inventor： STOJANOVIC, Vladimir, M. ,  HOROWITZ, Mark, A. ,  ZERBE, Jared, L. ,  BESSIOS, Anthony ,  HO, Andrew, C., C. ,  WEI, Jason, C. ,  TSANG, Grace ,  GARLEPP, Bruno, W.

IPC: H01L

CPC classification number: H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

Abstract: A receive circuit for receiving a signal transmitted via an electrical signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract translation: 用于接收通过电信号导体发送的信号的接收电路。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路从第一和第二采样电路接收第一和第二采样值，并根据先前产生的采样值选择作为选择的采样值输出的第一采样值或第二采样值。

公开(公告)号：WO0048370A2

公开(公告)日：2000-08-17

申请号：PCT/US0002507

申请日：2000-02-11

Applicant: ALTOCOM INC ,  GONIKBERG MARK

Inventor： GONIKBERG MARK

IPC: H03D1/00 ,  H03M13/39 ,  H03M13/41 ,  H04L25/03 ,  H04L25/49 ,  H04L25/497 ,  H04L27/00 ,  H04L27/06

CPC classification number: H04L25/03229 ,  H04L25/03267 ,  H04L2025/03369

Abstract: A reduced state maximum likelihood sequence estimator allows the use of improved equalization techniques that provides greatly improved performance for channels with severe attenuation and spectral nulls. The reduced state maximum likelihood sequence estimator retains kn states of a total number of K states, kn

Abstract translation: 缩减状态最大似然序列估计器允许使用改进的均衡技术，其为具有严重衰减和频谱零点的信道提供极大改进的性能。 缩减状态最大似然序列估计器保持K个状态的总数kn

公开(公告)号：WO0029860A2

公开(公告)日：2000-05-25

申请号：PCT/US9927057

申请日：1999-11-12

Applicant: BROADCOM CORP ,  HATAMIAN MEHDI

Inventor： HATAMIAN MEHDI

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H04B3/23 ,  H04B3/32 ,  H04L1/00 ,  H04L1/24 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  G01R31/00

CPC classification number: H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3012 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: The present invention is a method and a system for controlling a voltage at a node in a circuit such that the node is prevented from having an unknown floating voltage during a steady state of a clock signal. The circuit includes a transmission gate which has input and output terminals, and operates in response to a clock signal. The node is located proximal to the output terminal of the transmission gate. The method includes the operations of driving the node with an input signal when the transmission gate is open during a first steady state of the clock signal and pulling the node to a fixed voltage when the transmission gate is closed during a second steady state of the clock signal.

Abstract translation: 本发明是一种用于控制电路节点处的电压的方法和系统，使得节点在时钟信号的稳定状态期间被防止具有未知的浮动电压。 该电路包括具有输入和输出端的传输门，并响应时钟信号而工作。 节点位于传输门的输出端附近。 该方法包括在时钟信号的第一稳定状态期间传输门打开时驱动节点的操作，并且在时钟的第二稳定状态期间传输门关闭时将节点拉至固定电压 信号。

公开(公告)号：WO00028663A2

公开(公告)日：2000-05-18

申请号：PCT/US1999/026483

申请日：1999-11-09

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H04B3/23 ,  H04B3/32 ,  H04L1/00 ,  H04L1/24 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  H03H17/06 ,  H03H17/02

CPC classification number: H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: A digital filter has an input path and an output path and includes a set of delay elements and a number of taps. The taps couple the input path to the output path. Each of the taps has a coefficient, a multiplier and an adder. Each of the delay elements is disposed between two adjacent taps. The delay elements are placed in either the input path and the output path of the digital filter, such that the digital filter has fewer delay elements in the input path than a direct-form digital filter with the same number of taps in a direct-form structure, and has fewer delay elements in the output path than a transposed-form digital filter with the same number of taps in a transposed-form structure; and such that the digital filter has same transfer function as the direct-form digital filter and the transposed-form digital filter.

Abstract translation: 数字滤波器具有输入路径和输出路径，并且包括一组延迟元件和多个抽头。 抽头将输入路径耦合到输出路径。 每个抽头具有系数，乘数和加法器。 每个延迟元件设置在两个相邻的抽头之间。 延迟元件放置在数字滤波器的输入路径和输出路径中，使得数字滤波器在输入路径中具有比直接形式的数字滤波器更少的延迟元件，其具有相同数量的直接形式的抽头 结构，并且在转置形式结构中具有相同数量的抽头的转置形式的数字滤波器在输出路径中具有较少的延迟元件; 并且使得数字滤波器具有与直接形式的数字滤波器和转置形式的数字滤波器相同的传递函数。

公开(公告)号：WO2013190395A2

公开(公告)日：2013-12-27

申请号：PCT/IB2013/002081

申请日：2013-06-14

Applicant: MAGNACOM LTD.

Inventor： ELIAZ, Amir

IPC: H04L29/06

CPC classification number: H04L1/0041 ,  G06F11/10 ,  H04B1/0475 ,  H04B1/10 ,  H04B1/16 ,  H04B1/709 ,  H04B17/0085 ,  H04B17/15 ,  H04B17/29 ,  H04B2001/0416 ,  H04L1/0036 ,  H04L1/0048 ,  H04L1/005 ,  H04L1/0054 ,  H04L1/203 ,  H04L1/206 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/02 ,  H04L7/042 ,  H04L23/02 ,  H04L25/0236 ,  H04L25/03006 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03178 ,  H04L25/03197 ,  H04L25/03267 ,  H04L25/0328 ,  H04L25/03305 ,  H04L25/03318 ,  H04L25/03337 ,  H04L25/03343 ,  H04L25/03834 ,  H04L25/03885 ,  H04L25/03949 ,  H04L25/08 ,  H04L27/00 ,  H04L27/01 ,  H04L27/02 ,  H04L27/04 ,  H04L27/2278 ,  H04L27/36 ,  H04L27/366 ,  H04L27/368 ,  H04L27/38 ,  H04L2025/03369

Abstract: A transmitter may comprise a symbol mapping circuit that is configurable to operate in at least two configurations, wherein a first of the configurations of the symbol mapping circuit uses a first symbol constellation and a second of the configurations of the symbol mapping circuit uses a second symbol constellation. The transmitter may also comprise a pulse shaping circuit that is configurable to operate in at least two configurations, wherein a first of the configurations of the pulse shaping circuit uses a first set of filter taps and a second of the configurations of the pulse shaping circuit uses a second set of filter taps. The first set of filter taps may correspond to a root raised cosine (RRC) filter and the second set of filter taps corresponds to a partial response filter.

Abstract translation: 发射机可以包括可配置为以至少两种配置操作的符号映射电路，其中符号映射电路的第一配置使用第一符号星座，并且符号映射电路的配置中的第二配置使用第二符号 星座。 发射机还可以包括脉冲整形电路，其可被配置为以至少两种配置工作，其中脉冲整形电路的第一种配置使用第一组滤波器抽头，并且脉冲整形电路的第二种配置使用 第二组滤波器抽头。 第一组滤波器抽头可以对应于根升余弦（RRC）滤波器，并且第二组滤波器抽头对应于部分响应滤波器。

公开(公告)号：WO2011106052A1

公开(公告)日：2011-09-01

申请号：PCT/US2010/058088

申请日：2010-11-24

Applicant: RAMBUS INC. ,  LEIBOWITZ, Brian ,  KIM, Jaeha

Inventor： LEIBOWITZ, Brian ,  KIM, Jaeha

IPC: H04L27/01 ,  H03K7/02

CPC classification number: H04L25/03057 ,  H03M1/004 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/362 ,  H04L25/03146 ,  H04L25/03885 ,  H04L2025/03363 ,  H04L2025/03369

Abstract: A decision- feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.

Abstract translation: 在相同符号时间内，判决反馈均衡器（DFE）对M个参考采样模拟输入信号以产生M个推测采样。 在DFE中选择逻辑然后解码先前为先前符号时间分辨的N个比特，以选择M个推测样本之一作为当前分辨比特。 然后将当前解析的位存储为最近以前解析的位，以准备下一个符号时间。 选择逻辑可以是可编程的，以适应过程，环境和系统变化。

公开(公告)号：WO00065772A2

公开(公告)日：2000-11-02

申请号：PCT/US2000/011123

申请日：2000-04-24

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H04B3/23 ,  H04B3/32 ,  H04L1/00 ,  H04L1/24 ,  H04L7/00 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  H04L12/00

CPC classification number: H04L7/0062 ,  G01R31/3008 ,  G01R31/31715 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2025/03617

Abstract: A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals and diagnostics signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs, the status signals and diagnostics signals, to the DSP and the PCS.

Abstract translation: 一种用于控制多对千兆位收发器的操作的方法。 多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制接收来自串行管理模块的用户定义的输入以及来自DSP和PCS的状态信号和诊断信号​​，并根据用户定义的输入，状态信号和诊断信号​​产生控制信号到DSP和 PCS。

公开(公告)号：WO00046802A1

公开(公告)日：2000-08-10

申请号：PCT/JP2000/000544

申请日：2000-02-01

IPC: G11B20/10 ,  G11B20/18 ,  H03H15/00 ,  H03H21/00 ,  H04B3/06 ,  H04L25/03 ,  H04L25/497

CPC classification number: H04L25/497 ,  G11B20/10009 ,  H04L25/03038 ,  H04L2025/03369 ,  H04L2025/03477

Abstract: High-order partial response is equalized so that the equalization difference of an input signal having nonlinear distortion is a minimum so as to improve the characteristics of a reproduced signal. An input signal is subjected to high-order partial response equalization by a transversal filter (3), a tentative estimation value of an equalization target value is estimated by a tentative estimating circuit (4), the difference between the tentative estimation value and the input signal is detected by a difference detecting circuit (5), the difference between the tentative estimation value and the output signal of an analog-digital converter (1) is detected by an input distortion detecting circuit (7), the difference outputted from the difference detecting circuit (5) is monitored by an output distortion detecting circuit (6), the equalization target value is controlled by equalization target controlling means (8) so that the equalization difference is a minimum, and a tap coefficient is controlled by tap coefficient controlling means (10).

Abstract translation: 高阶部分响应被均衡，使得具有非线性失真的输入信号的均衡差最小，以便改善再现信号的特性。 通过横向滤波器（3）对输入信号进行高阶部分响应均衡，通过暂定估计电路（4）估计均衡目标值的暂定估计值，暂定估计值与输入之间的差 通过差分检测电路（5）检测信号，通过输入失真检测电路（7）检测模拟数字转换器（1）的暂定估计值与输出信号之间的差异，从差值输出的差值 检测电路（5）由输出失真检测电路（6）监视，均衡目标值由均衡目标控制装置（8）控制，使得均衡差最小，抽头系数由抽头系数控制 手段（10）。

公开(公告)号：WO00028691A2

公开(公告)日：2000-05-18

申请号：PCT/US1999/026493

申请日：1999-11-09

IPC: G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H04B3/23 ,  H04B3/32 ,  H04L1/00 ,  H04L1/24 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497

CPC classification number: H04L7/0062 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages: a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

Abstract translation: 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段：第一阶段补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二阶段补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。