公开(公告)号：WO2022216341A1

公开(公告)日：2022-10-13

申请号：PCT/US2022/012541

申请日：2022-01-14

申请人： SANDISK TECHNOLOGIES LLC

发明人： SHAO, Shiqian ,  TOYAMA, Fumiaki

IPC分类号： H01L27/11526 ,  H01L27/11551 ,  H01L27/11575

摘要： To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

公开(公告)号：WO2022240456A1

公开(公告)日：2022-11-17

申请号：PCT/US2022/013595

申请日：2022-01-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： SHAO, Shiqian ,  TOYAMA, Fumiaki ,  RABKIN, Peter

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L28/60 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19041 ,  H01L2924/19104

摘要： A semiconductor structure includes a bonded assembly of a first semiconductor die including first metal bonding pads and a second semiconductor die including second metal bonding pads, and a capacitor structure including a first electrode, a second electrode, and a node dielectric. The first electrode includes first bonded pairs of metal bonding pads. The second electrode includes second bonded pairs of metal bonding pads. The node dielectric includes portions dielectric material layers laterally surrounding the metal bonding pads.

公开(公告)号：WO2022216342A1

公开(公告)日：2022-10-13

申请号：PCT/US2022/012546

申请日：2022-01-14

申请人： SANDISK TECHNOLOGIES LLC

发明人： SHAO, Shiqian ,  TOYAMA, Fumiaki

IPC分类号： G11C16/04 ,  G11C8/08 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11578

摘要： To overcome a shortage of area for horizontal metal lines to connect word line switch transistors to corresponding word lines and for pass through signal lines, it is proposed to implement multiple architectures for the word line hook up regions. For example, some areas of a die will be designed to provide extra horizontal metal lines to connect word line switch transistors to word lines and other areas of the die will be designed to provide extra pass through signal lines.

公开(公告)号：WO2022216340A1

公开(公告)日：2022-10-13

申请号：PCT/US2022/012535

申请日：2022-01-14

申请人： SANDISK TECHNOLOGIES LLC

发明人： SHAO, Shiqian ,  TOYAMA, Fumiaki ,  MIZUTANI, Yuki ,  DUNGA, Mohan ,  RABKIN, Peter

IPC分类号： G11C16/12 ,  G11C16/08 ,  G11C8/08

摘要： A non-volatile memory includes a non-volatile memory array comprising blocks of non-volatile memory cells, bit lines connected to the memory cells and word lines connected to the memory cells. Word line switch transistors connect the word lines to voltage sources. The word line switch transistors are positioned in triple wells. Multiple triple wells are utilized and the word line switch transistors are grouped into triple wells based on word line voltage ranges used during the programming process. In one embodiment, for a given block, the word line switch transistors connected to data word lines are positioned in a first triple well and the word line switch transistors connected to selection and dummy word lines are positioned in a second triple well. This structure allows the triple wells to be biased differently.