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公开(公告)号：WO2022031354A1
公开(公告)日：2022-02-10
申请号：PCT/US2021/035612
申请日：2021-06-03
IPC分类号： H01L21/8234 , H01L27/11524 , H01L27/11578 , H01L29/10 , H01L29/04 , H01L29/792
摘要： A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.
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2.发明申请
公开(公告)号：WO2021262249A1
公开(公告)日：2021-12-30
申请号：PCT/US2021/012421
申请日：2021-01-07
IPC分类号： H01L21/8252 , H01L21/02 , H01L21/683 , H01L27/11578 , H01L21/76254 , H01L21/7806 , H01L25/00
摘要： A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.
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3.发明申请
公开(公告)号：WO2021242328A1
公开(公告)日：2021-12-02
申请号：PCT/US2021/012408
申请日：2021-01-07
IPC分类号： H01L29/205 , H01L27/11582 , H01L27/11556 , H01L27/11524 , H01L21/28 , H01L21/02 , H01L29/06
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.
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4.发明申请
公开(公告)号：WO2021015827A1
公开(公告)日：2021-01-28
申请号：PCT/US2020/024138
申请日：2020-03-23
发明人： WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC分类号： H01L25/065 , H01L23/31 , H01L23/48 , H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.
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公开(公告)号：WO2017172072A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/017630
申请日：2017-02-13
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5635 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16
摘要： Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.
摘要翻译： 描述了通过利用NAND串的不同部分之间的一个或多个层选择门晶体管来提高非易失性存储器的性能的系统和方法。 第一存储器串层可以包括可以被编程以存储第一组数据的第一组存储器单元晶体管，并且第二存储器串层可以包括被布置在第一组晶体管上方的第二组存储器单元晶体管，以及 其可以被编程为存储第二组数据。 在第一组存储器单元晶体管和第二组存储器单元晶体管之间可以包括与第一组存储器单元晶体管和第二组存储器单元晶体管串联的层选择栅极晶体管。 层选择栅晶体管可以包括可编程晶体管或不可编程晶体管。
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6.发明申请
公开(公告)号：WO2022231669A1
公开(公告)日：2022-11-03
申请号：PCT/US2022/012172
申请日：2022-01-12
发明人： HOU, Lin , RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L23/00 , H01L23/495
摘要： A bonded assembly of a first semiconductor die and a second semiconductor die includes first and second semiconductor dies. The first semiconductor die includes first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first metal bonding pads laterally surrounded by a semiconductor material layer. The second semiconductor die includes second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second metal bonding pads that include primary metal bonding pads and auxiliary metal bonding pads. The auxiliary metal bonding pads are bonded to the semiconductor material layer through metal-semiconductor compound portions formed by reaction of surface portions of the semiconductor material layer and an auxiliary metal bonding pad. The primary metal bonding pads are bonded to the first metal bonding pads by metal-to-metal bonding.
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7.发明申请
公开(公告)号：WO2021177990A1
公开(公告)日：2021-09-10
申请号：PCT/US2020/037619
申请日：2020-06-12
发明人： WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC分类号： H01L21/768 , H01L21/02 , H01L23/495 , B23K26/36 , H01L27/11582 , H01L27/11556
摘要： A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.
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8.发明申请
公开(公告)号：WO2021107971A1
公开(公告)日：2021-06-03
申请号：PCT/US2020/023493
申请日：2020-03-19
发明人： WU, Chen , RABKIN, Peter , HIGASHITANI, Masaaki
IPC分类号： H01L25/065 , H01L23/31 , H01L23/00 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： A first semiconductor die includes first bonding pads. The first bonding pads include proximal bonding pads embedded within a first bonding dielectric layer and distal bonding pads having at least part of the sidewall that overlies the first bonding dielectric layer. A second semiconductor die includes second bonding pads. The second bonding pads are bonded to the proximal bonding pads and the distal bonding pads. The proximal bonding pads are bonded to a respective one of a first subset of the second bonding pads at a respective horizontal bonding interface and the distal bonding pads are bonded to a respective one of a second subset of the second bonding pads at a respective vertical bonding interface at the same time. Dielectric isolation structures may vertically extend through the second bonding dielectric layer of the second semiconductor die and contact the first bonding dielectric layer.
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公开(公告)号：WO2021040809A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/026106
申请日：2020-04-01
发明人： WU, Chen , RABKIN, Peter , CHEN, Yangyin , HIGASHITANI, Masaaki
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L27/11524 , H01L27/11529 , H01L27/11556
摘要： A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.
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公开(公告)号：WO2016191155A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/032927
申请日：2016-05-17
IPC分类号： H01L29/423 , H01L21/28 , H01L29/51 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/1157 , H01L29/4234 , H01L29/513 , H01L29/517
摘要： A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to S13N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
摘要翻译： 公开了具有高k电荷存储区域的存储单元以及制造方法的非易失性存储装置。 电荷存储区域具有三层或更多层介电材料。 至少一层是高k材料。 与S13N4相比，高k层具有更高的陷阱密度。 电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合，这可以提高存储单元电流，编程速度和擦除速度。 电荷存储区具有高 - 低 - 高导带偏移，这可以改善数据保留。 电荷存储区域具有低 - 高 - 低价带偏移，这可以改善擦除。
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