公开(公告)号：WO2015004541A2

公开(公告)日：2015-01-15

申请号：PCT/IB2014002315

申请日：2014-06-23

Applicant: SANMINA CORP

Inventor： IKETANI SHINICHI ,  KERSTEN DALE

IPC: H05K3/10

CPC classification number: H05K3/429 ,  H05K3/427 ,  H05K2203/308 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975 ,  Y10T428/31529 ,  Y10T428/31544 ,  Y10T428/31678 ,  Y10T428/31681

Abstract: A core or sub-composite structure is provided including a dielectric layer between a first conductive film and a second conductive film. The first conductive film may include a first peelable/removable cover layer formed on or coupled to a first conductive layer. The second conductive film may include a second peelable/removable cover layer formed on or coupled to a second conductive layer.

Abstract translation: 提供了一种芯或子复合结构，包括在第一导电膜和第二导电膜之间的介电层。 第一导电膜可以包括形成在第一导电层上或耦合到第一导电层的第一可剥离/可移除覆盖层。 第二导电膜可以包括形成在第二导电层上或耦合到第二导电层的第二可剥离/可移除覆盖层。

公开(公告)号：WO2015112758A9

公开(公告)日：2016-01-14

申请号：PCT/US2015012523

申请日：2015-01-22

Applicant: SANMINA CORP

Inventor： THOMAS DOUGLAS WARD ,  IKETANI SHINICHI ,  KERSTEN DALE

IPC: H05K3/40 ,  H05K3/42

CPC classification number: H05K3/429 ,  H05K1/0216 ,  H05K3/24 ,  H05K2201/09845 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/072 ,  H05K2203/0723

Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.

Abstract translation: 印刷电路板（PCB）技术领域本发明涉及印刷电路板（PCB），更具体地涉及在印刷电路板（PCB）中形成高纵横比通孔和高精度短截线的方法。 高精度残留物去除过程可用于去除长桩和短桩。 在该方法中，使用不同直径的钻头从印刷电路板的上表面和/或下表面钻出不同直径和深度的多个孔。

公开(公告)号：WO2014145387A3

公开(公告)日：2015-01-29

申请号：PCT/US2014030144

申请日：2014-03-17

Applicant: SANMINA CORP

Inventor： IKETANI STEVE ,  KERSTEN DALE

IPC: H05K3/46 ,  H05K3/42

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract translation: 提供了具有选择性地定位在第一介电层中的第一电介质层和第一电镀抗蚀剂的多层印刷电路板。 可以将第二电镀抗蚀剂选择性地定位在第一电介质层或第二电介质层中，第二电镀抗蚀剂与第一电镀抗蚀剂分离。 通孔延伸穿过第一电介质层，第一电镀抗蚀剂和第二电镀抗蚀剂。 除了沿第一电镀抗蚀剂和第二电镀抗蚀剂之间的长度之外，通孔的内表面镀有导电材料。 这形成了具有与第二通孔段电隔离的第一通路段的分隔电镀通孔。