公开(公告)号：WO2018104828A1

公开(公告)日：2018-06-14

申请号：PCT/IB2017/057512

申请日：2017-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： INOUE, Hiroki ,  KUROKAWA, Yoshiyuki ,  NAKAGAWA, Takashi ,  AKASAWA, Fumika

IPC: H04N19/625 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/786 ,  H03M7/30 ,  H04N19/42

CPC classification number: H04N19/625 ,  G05F1/46 ,  G05F3/24 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/78648 ,  H03M7/30 ,  H04N19/42

Abstract: To provide a decoder whose area is reduced. The decoder includes an inverse discrete cosine transform (IDCT) circuit. The IDCT circuit includes a multiplier circuit. The multiplier circuit includes an arithmetic circuit that multiplies a first current and a second current, a current generator that generates the first current, and a digital-analog converter that generates a reference current used by the current generator. The current generator includes a current mirror circuit (CM circuit) including first and second transistors, a third transistor, a switch that controls the current output, and first and second memory circuits. The reference current of the CM circuit is input to a drain of the first transistor, and a current which copies the reference current is output from a drain of the second transistor. A drain of the third transistor is electrically connected to the drain of the second transistor. The switch controls the first current output.