公开(公告)号：WO2018182714A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025503

申请日：2017-03-31

申请人： INTEL CORPORATION

发明人： SHARMA, Abhishek, A. ,  LE, Van H. ,  DEWEY, Gilbert ,  GHANI, Tahir ,  KAVALIEROS, Jack, T.

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/66742 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78609

摘要： Embodiments herein describe techniques for a semiconductor device including a top-gated TFT having high mobility, while keeping the leakage low. Embodiments may include a dielectric layer above a substrate and multiple channel layers above the dielectric layer. For example, a first channel layer including a first material may be above the dielectric layer, and a second channel layer including a second material may be above the first channel layer, wherein the first material may have a lower leakage than the second material, and the second material may have a higher mobility than the first material. Embodiments may further include a source electrode, a drain electrode, and a gate electrode above the second channel layer. Other embodiments may be described and/or claimed.

公开(公告)号：WO2018063160A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/053976

申请日：2016-09-27

申请人： INTEL CORPORATION

发明人： RADOSAVLJEVIC, Marko ,  DASGUPTA, Sansaptak ,  THEN, Han Wui

IPC分类号： H01L29/778 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/2003 ,  H01L21/76898 ,  H01L21/823807 ,  H01L21/8258 ,  H01L23/481 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1218 ,  H01L27/1225

摘要： Methods and apparatus to form GaN-based transistors during backend-of-line processing are disclosed. An example integrated circuit includes a first transistor formed on a first semiconductor substrate. The example integrated circuit includes a dielectric material formed on the first semiconductor substrate. The dielectric material extends over the first transistor. The example integrated circuit further includes a second semiconductor substrate formed on the dielectric material. The example integrated circuit also includes a second transistor formed on the second semiconductor substrate.

摘要翻译： 公开了在后端处理期间形成GaN基晶体管的方法和设备。 示例集成电路包括形成在第一半导体衬底上的第一晶体管。 示例集成电路包括形成在第一半导体衬底上的电介质材料。 介电材料在第一晶体管上方延伸。 示例集成电路进一步包括形成在电介质材料上的第二半导体衬底。 示例集成电路还包括形成在第二半导体衬底上的第二晶体管。

公开(公告)号：WO2017172154A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/019575

申请日：2017-02-27

申请人： RAYTHEON COMPANY

发明人： LAROCHE, Jeffrey, R. ,  IP, Kelly, P. ,  KAZIOR, Thomas, E.

IPC分类号： H01L21/768 ,  H01L21/683 ,  H01P3/08 ,  H01P11/00

CPC分类号： H01L29/78681 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/8258 ,  H01L23/66 ,  H01L29/78603 ,  H01L2221/68327 ,  H01L2223/6627 ,  H01P3/082 ,  H01P11/003

摘要： A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

摘要翻译： 一种用于提供半导体结构的方法包括：提供具有以下层的结构：包括硅的层，诸如硅或碳化硅层; 结合结构; 以及硅层，所述接合结构设置在所述硅层和所述硅层之间，所述硅层比所述硅层厚; 以及设置在包含硅的层的上表面上的III-V族层; 在所述III-V层中形成III-V族器件以及连接到所述器件的带状导体; 去除硅层和键合结构以暴露含硅层的底表面; 以及在包含硅的层的暴露的底表面上形成接地平面导体，以与带状导体和接地平面导体一起提供微带传输线。

公开(公告)号：WO2017137864A1

公开(公告)日：2017-08-17

申请号：PCT/IB2017/050471

申请日：2017-01-30

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： YAMAZAKI, Shunpei ,  ENDO, Yuta ,  KATO, Kiyoshi ,  OKAMOTO, Satoru

IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H01L27/108 ,  H01L27/146 ,  H01L29/786

CPC分类号： H01L27/1207 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

摘要： A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

摘要翻译： 提供适合小型化和高集成度的高度可靠的半导体器件。 该半导体器件包括第一绝缘体; 在第一绝缘体上方的晶体管; 晶体管之上的第二绝缘体; 嵌入第二绝缘体中的开口中的第一导体; 第一导体上的阻挡层; 在所述第二绝缘体上且在所述阻挡层上方的第三绝缘体; 以及第三绝缘体上的第二导体。 第一绝缘体，第三绝缘体和阻挡层具有对氧和氢的阻隔性。 第二绝缘体包括过量氧区域。 晶体管包括氧化物半导体。 阻挡层，第三绝缘体和第二导体起到电容器的作用。

公开(公告)号：WO2017111884A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/066983

申请日：2015-12-21

申请人： INTEL CORPORATION

发明人： THEN, Han Wui ,  DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  SUNG, Seung Hoon ,  GARDNER, Sanaz

IPC分类号： H01L25/16 ,  H01L27/04

CPC分类号： H01L25/16 ,  H01L21/8258 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/7786

摘要： Techniques are disclosed for forming monolithic integrated circuit semiconductor structures that include a III-V portion implemented with III-N semiconductor materials, such as gallium nitride, indium nitride, aluminum nitride, and mixtures thereof. The disclosed semiconductor structures may further include a CMOS portion implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). The disclosed techniques can be used to form highly-efficient envelope tracking devices that include a voltage regulator and a radio frequency (RF) power amplifier that may both be located on the III-N portion of the semiconductor structure. Either of the CMOS or III-N portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of a III-N voltage regulator and RF power amplifier along with column IV CMOS devices on a single substrate.

摘要翻译： 公开了用于形成单片集成电路半导体结构的技术，所述单片集成电路半导体结构包括用III-N半导体材料（例如氮化镓，氮化铟，氮化铝及其混合物）实现的III-V部分。 所公开的半导体结构还可以包括用从周期表的IV族中选择的半导体材料实现的CMOS部分，诸如硅，锗和/或硅锗（SiGe）。 所公开的技术可以用于形成包括电压调节器和射频（RF）功率放大器的高效包络追踪设备，所述电压调节器和射频（RF）功率放大器都可以位于半导体结构的III-N部分上。 在某种程度上，CMOS或III-N部分中的任何一个都可以是底层衬底的原生材料。 例如，这些技术可用于III-N电压调节器和RF功率放大器的系统级芯片集成以及单列衬底上的列IV CMOS器件。

公开(公告)号：WO2017111871A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000497

申请日：2015-12-24

申请人： INTEL CORPORATION

发明人： DASGUPTA, Sansatptak ,  THEN, Han Wui ,  RADOSAVLJEVIC, Marko

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/78

摘要： Transistors including doped heteroepitaxial III-N source/drain crystals. In embodiments, transistors including a group IV or group III-V channel crystal employ n+ doped III-N source/drain structures on either side of a gate stack. Lateral tensile strain of the channel crystal may result from lattice mismatch between the channel crystal and the III-N source/drain crystals. In embodiments, an amorphous material is employed to limit growth of III-N material to only a single channel crystal facet, allowing a high quality monocrystalline source/drain to form that is capable of sustaining significant stress. In some embodiments, an n+ III-N source/drain crystal is grown on a (110) or (111) surface of a silicon channel crystal fabricated into a fin structure to form a tensile strained NMOS finFET.

摘要翻译： 包括掺杂异质外延III-N源极/漏极晶体的晶体管。 在实施例中，包括IV族或III-V族沟道晶体的晶体管在栅极堆叠的任一侧上采用n +掺杂的III-N源极/漏极结构。 沟道晶体的横向拉伸应变可由沟道晶体与III-N源极/漏极晶体之间的晶格失配导致。 在实施例中，采用无定形材料来将III-N材料的生长限制为仅单一沟道晶面，从而允许形成能够承受显着应力的高质量单晶源极/漏极。 在一些实施例中，n + III-N源极/漏极晶体在制造成鳍状结构的硅沟道晶体的（110）或（111）表面上生长以形成拉伸应变NMOS finFET。

公开(公告)号：WO2017052594A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052253

申请日：2015-09-25

申请人： INTEL CORPORATION

发明人： GLASS, Glenn A. ,  SON, Il-seok ,  MURTHY, Anand S. ,  FISCHER, Paul B.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/785

摘要： Techniques are disclosed for semiconductor device wafer bonding integration. The wafer bonding integration employs device-quality embedded epitaxial layers (e.g., high-quality single-crystal semiconductor material layers) from which one or more devices (e.g., transistors) can be formed, enabling vertical 3D integration schemes. The integration techniques include the ability to produce transistors and back-end stacks on very thin substrates, where the substrate is of device-level quality. The techniques include forming a multilayer substrate including a bulk wafer, a sacrificial layer, and a device-quality layer from which one or more transistors are formed. After back-end processing, the transistors can be bonded to a host wafer that also includes transistors, such that the transistors are stacked in a vertical fashion. After the bonding process, the bulk wafer of the multilayer substrate can be removed from the transistor that was bonded, by at least partially removing the sacrificial layer of the multilayer substrate.

摘要翻译： 公开了用于半导体器件晶片结合集成的技术。 晶片接合集成采用了能够形成一个或多个器件（例如晶体管）的器件质量的嵌入式外延层（例如高质量单晶半导体材料层），从而能够实现垂直3D集成方案。 集成技术包括在非常薄的衬底上生产晶体管和后端堆叠的能力​​，其中衬底具有器件级质量。 这些技术包括形成包括体晶片，牺牲层和形成一个或多个晶体管的器件质量层的多层衬底。 在后端处理之后，晶体管可以结合到还包括晶体管的主晶片，使得晶体管以垂直方式堆叠。 在接合工艺之后，可以通过至少部分去除多层基板的牺牲层，从结合的晶体管中去除多层基板的体晶片。

公开(公告)号：WO2017052587A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/052223

申请日：2015-09-25

申请人： INTEL CORPORATION

发明人： GLASS, Glenn A. ,  BRAZIER, Mark R. ,  MURTHY, Anand S. ,  GHANI, Tahir ,  LOH, Owen Y.

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  B82Y10/00 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/7391 ,  H01L29/775

摘要： Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.

摘要翻译： 公开了用于钝化晶体管沟道区界面的技术。 在一些情况下，待钝化的晶体管沟道区界面包括半导体沟道和栅极电介质之间的界面和/或子沟道半导体材料与隔离材料之间的界面。 例如，氧化铝（也称为氧化铝）层可以用于钝化通道/栅极界面，其中沟道材料包括硅锗，锗或III-V材料。 这些技术可用于降低通道/栅极接口处的接口陷阱密度，并且这些技术也可用于在栅极第一和栅极末端工艺流程中钝化沟道/栅极界面。 这些技术还可以在子通道/隔离接口处包括附加的钝化层，以便例如避免产生额外的寄生电容损失。

公开(公告)号：WO2017052552A1

公开(公告)日：2017-03-30

申请号：PCT/US2015/051965

申请日：2015-09-24

申请人： INTEL CORPORATION

发明人： DASGUPTA, Sansaptak ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  PILLARISETTY, Ravi ,  JUN, Kimin ,  MORROW, Patrick ,  RAO, Valluri R. ,  FISCHER, Paul B. ,  CHAU, Robert S.

IPC分类号： H01L21/8238

CPC分类号： H01L21/8258 ,  H01L27/0688

摘要： The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

摘要翻译： 各种半导体的电学和电化学性质可能限制了一种或多种目的的各种半导体材料的有用性。 包含多个GaN功率管理集成电路（PMIC）管芯的完成的氮化镓（GaN）半导体层可以结合到包含多个互补金属氧化物（CMOS）控制电路管芯的完整的硅半导体层。 完成的GaN层和完成的硅层可以是全尺寸（例如，300mm）。 可以使用层转移操作来将完成的GaN层结合到完成的硅层。 层转移操作可以在全尺寸晶片上进行。 在切割全尺寸晶片之后，可以生产各自具有转移到硅晶片的GaN管芯层的大量多层管芯。

公开(公告)号：WO2017014031A1

公开(公告)日：2017-01-26

申请号：PCT/JP2016/069726

申请日：2016-06-27

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： TEO, Koon Hoo ,  ZHANG, Yuhao

IPC分类号： H01L21/8258 ,  H01L27/06 ,  H01L27/085 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L29/7787 ,  H01L21/8258 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/092 ,  H01L29/205 ,  H01L29/66462

摘要： A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel (140) formed in a first layer (173) made of a first material and at least one p-type channel (150) formed in a second layer (171) made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability.

摘要翻译： 半导体器件包括形成多个载流子通道的层状结构，该沟道包括形成在由第一材料制成的第一层（173）中的至少一个n型沟道（140）和形成在第二层中的至少一个p型沟道（150） 由第二材料制成的层（171）和用于在载体通道中提供和控制载流子电荷的一组电极。 第一材料与第二材料不同，并且选择第一和第二材料使得n型沟道和p型沟道具有可比的开关频率和电流能力。