公开(公告)号：WO03005452A3

公开(公告)日：2003-09-04

申请号：PCT/US0220301

申请日：2002-06-21

Applicant: SILICONIX INC

Inventor： DARWISH MOHAMED N

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/2253 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7813

Abstract: A trench MOSFET (30) is formed in a structure which includes a P-type epitaxial layer (34) overlying an N+ substrate (32). An N-type dopant is implanted through the bottom of the trench (35) into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region (33) extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region (34A) may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract translation: 沟槽MOSFET（30）形成为包括覆盖在N +衬底（32）上的P型外延层（34）的结构。 通过沟槽（35）的底部将N型掺杂剂注入到P外延层中以在沟槽下形成掩埋层，并且在上扩散步骤之后，N漏极漂移区域（33）在 N +衬底和沟槽的底部。 结果是沟槽下方的N型掺杂剂的更可控的掺杂分布。 也可以通过将P型掺杂剂注入到外延层中来形成体区（34A），在这种情况下，外延层的背景掺杂可以是轻掺杂的P型或N型。 根据本发明构造的MOSFET可以具有降低的阈值电压和导通电阻以及增加的穿通击穿电压。

公开(公告)号：WO03015180A2

公开(公告)日：2003-02-20

申请号：PCT/US0224782

申请日：2002-08-05

Applicant: SILICONIX INC

Inventor： DARWISH MOHAMED N ,  YUE CHRISTINA ,  GILES FREDERICK P ,  LUI KAM HONG ,  CHEN KUO-IN ,  TERRILL KYLE ,  PATTANAYAK DEVA N

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/0878 ,  H01L29/7813

Abstract: A trench MOSFET (40) includes active corner regions (25) and a thick insulative layer (33) centrally located at the bottom of the trench (19). A thin gate insulative layer (15) lines the sidewall and peripheral portion of the bottom surface of the trench (19). A gate (14) fills the trench, adjacent to the thin insulative layer (15). The gate (14) is adjacent to the sides and top of the thick insulative layer (33). The thick insulative layer (33) separates the gate (14) from the drain conductive region (13) at the bottom of the trench (19) yielding a reduced gate-to-drain capacitance and making the MOSFET (40) particularly suitable for high frequency applications.

Abstract translation: 沟槽MOSFET（40）包括中心位于沟槽（19）的底部的有源角区域（25）和厚绝缘层（33）。 薄栅绝缘层（15）将沟槽（19）的底表面的侧壁和周边部分排列。 栅极（14）填充与薄绝缘层（15）相邻的沟槽。 栅极（14）与厚绝缘层（33）的侧面和顶部相邻。 厚的绝缘层（33）在沟槽（19）的底部处将栅极（14）与漏极导电区域（13）分离，产生降低的栅极 - 漏极电容，并使MOSFET（40）特别适用于高 频率应用。