POLISHING STOP LAYER(S) FOR PROCESSING ARRAYS OF SEMICONDUCTOR ELEMENTS
    1.
    发明申请
    POLISHING STOP LAYER(S) FOR PROCESSING ARRAYS OF SEMICONDUCTOR ELEMENTS 审中-公开
    抛光停止层(S)用于处理半导体元件阵列

    公开(公告)号:WO2017019134A1

    公开(公告)日:2017-02-02

    申请号:PCT/US2016/027445

    申请日:2016-04-14

    CPC classification number: H01L43/12 H01L27/222 H01L43/02 H01L43/08

    Abstract: Described embodiments can be used in semiconductor manufacturing and employ materials with high and low polish rates to help determine a precise polish end point that is consistent throughout a wafer and that can cease polishing prior to damaging semiconductor elements. The height of the low polish rate material between the semiconductor elements is used as the polishing endpoint. Because the low polish rate material slows down the polishing process, it is easy to determine an end point and avoid damage to the semiconductor elements. An additional or alternative etch end point can be a thin layer of material that provides a very clear spectroscopy signal when it has been exposed, allowing the etch process to cease.

    Abstract translation: 描述的实施例可以用于半导体制造并且使用具有高和低抛光速率的材料来帮助确定在整个晶片上是一致的精确抛光终点并且可以在破坏半导体元件之前停止抛光。 半导体元件之间的低抛光速率材料的高度被用作抛光终点。 由于低抛光速率材料会降低抛光过程,因此很容易确定终点并避免损坏半导体元件。 额外的或替代的蚀刻终点可以是薄的材料层,当已经暴露时提供非常清楚的光谱信号,允许蚀刻过程停止。

Patent Agency Ranking