公开(公告)号：WO2019094545A1

公开(公告)日：2019-05-16

申请号：PCT/US2018/059749

申请日：2018-11-08

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： NAGEL, Kerry Joseph ,  AGGARWAL, Sanjeev ,  DESHPANDE, Sarin A.

IPC: H01L27/22 ,  H01L43/12

CPC classification number: H01L27/226 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: The disclosed integrated circuit device (100) includes a memory portion (120) and a logic portion (110). The memory portion includes magnetoresistive devices (210), preferably magnetic tunnel junctions (250), and metal conductors (230, 260, 270, 280) separated by a first interlayer dielectric (ILD) material (320, 350, 380) which is a low-k ILD or an ultra low-k ILD. The logic portion includes logic circuits and metal conductors (150, 154, 156, 158) separated by a second ILD which may be different from the first ILD. Corresponding methods of fabricating the device are disclosed as well.

公开(公告)号：WO2017131894A1

公开(公告)日：2017-08-03

申请号：PCT/US2016/067444

申请日：2016-12-19

Applicant: SPIN TRANSFER TECHNOLOGIES, INC.

Inventor： PINARBASI, Mustafa Michael ,  KARDASZ, Bartlomiej Adam

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be comprised of a layer of CoFeB ferromagnetic material.

Abstract translation: 公开了一种磁阻随机存取存储器（MRAM）器件。 本文所述的器件在磁隧道结的自由层上具有热稳定性增强层。 热稳定增强层提高了自由层的热稳定性，增加了自由层的磁矩，同时也不会导致自由层的磁性方向处于平面状态。 热稳定性增强层可以由一层CoFeB铁磁材料构成。

公开(公告)号：WO2017006210A1

公开(公告)日：2017-01-12

申请号：PCT/IB2016/053820

申请日：2016-06-27

Applicant: CROCUS TECHNOLOGY SA

Inventor： STAINER, Quentin

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic memory device (100) comprising a plurality of magnetic units (1), each unit including a first and second magnetic tunnel junctions (2, 2') electrically connecting in series by a current line (3) and a strap (7), the two junctions (2, 2') comprising a first and second storage layer (23, 23') having a first and second storage magnetization (230, 230') respectively and a first and second sense magnetic layer (21, 21') having a first and second senses magnetization (210, 210') respectively; a field line (4) configured to provide an input signal (41) generating a first and second magnetic field (42, 42') for varying the first and second sense magnetization (210, 210'); each magnetic unit (1) being provided with a data state such that the first and second storage magnetizations (230, 230') are aligned in opposed directions; the first and second magnetic field (42, 42') being adapted for varying respectively the first and second sense magnetization (210, 210') in a first and second direction opposed to the first direction.

Abstract translation: 一种包括多个磁性单元（1）的磁存储器件（100），每个单元包括通过电流线（3）和带子（7）串联电连接的第一和第二磁隧道结（2,2'）， 包括分别具有第一和第二存储磁化（230,230'）的第一和第二存储层（23,23'）的两个结（2,2'）和第一和第二感测磁性层（21,21'）， ）分别具有第一和第二感测磁化（210,210'）; （4），被配置为提供产生用于改变所述第一和第二感测磁化（210,210'）的第一和第二磁场（42,42'）的输入信号（41）。 每个磁单元（1）被提供有数据状态，使得第一和第二存储磁化（230,230'）在相对的方向上排列; 第一和第二磁场（42,42'）适于在与第一方向相反的第一和第二方向上分别改变第一和第二感测磁化（210,210'）。

公开(公告)号：WO2016204757A1

公开(公告)日：2016-12-22

申请号：PCT/US2015/036302

申请日：2015-06-17

Applicant: INTEL CORPORATION ,  ROMERO, Patricio, E. ,  PLOMBON, John, J.

Inventor： ROMERO, Patricio, E. ,  PLOMBON, John, J.

IPC: H01L21/3065

CPC classification number: H01L21/32135 ,  H01L21/28079 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Transition metal dry etch by atomic layer removal of oxide layers for device fabrication, and the resulting devices, are described. In an example, a method of etching a film includes reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species. The method also includes removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species. The method also includes reacting the oxidized surface layer of the transition metal species with a molecular etchant. The method also includes removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.

Abstract translation: 描述了通过用于器件制造的氧化物层的原子层去除的过渡金属干法蚀刻以及所得到的器件。 在一个实例中，蚀刻膜的方法包括使含过渡金属的膜的过渡金属物质的表面层与分子氧化物物质反应。 该方法还包括除去反应的分子氧化剂物质的挥发性碎片以提供过渡金属物质的氧化表面层。 该方法还包括使过渡金属物质的氧化表面层与分子蚀刻剂反应。 该方法还包括通过挥发除去过渡金属物质的反应氧化表面层和反应的分子蚀刻剂。

公开(公告)号：WO2016137730A1

公开(公告)日：2016-09-01

申请号：PCT/US2016/016939

申请日：2016-02-08

Applicant: QUALCOMM INCORPORATED

Inventor： LU, Yu ,  ZHU, Xiaochun ,  KANG, Seung; Hyuk

IPC: H01L27/22 ,  H01L43/12

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) bit cells (200) employing source lines (204) and/or bit lines (206) disposed in multiple, stacked metal layers to reduce MRAM bit cell resistance are disclosed. Related methods and systems are also disclosed. In aspects disclosed herein, MRAM bit cells are provided in a memory array. The MRAM bit cells are fabricated in an integrated circuit (IC) (202) with source lines and/or bit lines formed by multiple, stacked metal layers disposed above a semiconductor layer (210) to reduce the resistance of the source lines. In this manner, if node size in the IC is scaled down, the resistance of the source lines and/or the bit lines can be maintained or reduced to avoid an increase in drive voltage that generates a write current for write operations for the MRAM bit cells.

Abstract translation: 公开了使用设置在多个堆叠金属层中的源极线（204）和/或位线（206）的磁性随机存取存储器（MRAM）位单元（200）来降低MRAM位单元电阻。 还公开了相关方法和系统。 在本文公开的方面，MRAM位单元被提供在存储器阵列中。 在集成电路（IC）（202）中制造MRAM位单元，源极线和/或位线由设置在半导体层（210）上方的多个堆叠的金属层形成，以减小源极线的电阻。 以这种方式，如果IC中的节点尺寸按比例缩小，则可以维持或减小源极线和/或位线的电阻，以避免产生用于MRAM位的写入操作的写入电流的驱动电压的增加 细胞。

公开(公告)号：WO2016114718A1

公开(公告)日：2016-07-21

申请号：PCT/SG2015/050520

申请日：2015-12-31

Applicant: AGENCY FOR SCIENCE,TECHNOLOGY AND RESEARCH

Inventor： FOONG, Huey Chian ,  LI, Fei

IPC: H01L27/105 ,  H01L27/24 ,  G11C11/02 ,  G11C11/15 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C5/025 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1693 ,  H01L27/222 ,  H01L27/228

Abstract: According to various embodiments, there is provided a memory device including at least one sense amplifier having a first side and a second side, wherein the second side opposes the first side; a first array including a plurality of memory cells arranged at the first side; a second array including a plurality of memory cells arranged at the second side; a first row including a plurality of mid-point reference units arranged at the first side; and a second row including a plurality of mid-point reference units arranged at the second side, wherein each mid-point reference unit of the first row is configured to generate a first reference voltage, and wherein each mid-point reference unit of the second row is configured to generate a second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the first array based on the second reference voltage; wherein the sense amplifier is configured to determine a resistance state of a memory cell of the second array based on the first reference voltage.

Abstract translation: 根据各种实施例，提供了一种存储器件，其包括具有第一侧和第二侧的至少一个读出放大器，其中第二侧与第一侧相对; 包括布置在第一侧的多个存储单元的第一阵列; 包括布置在第二侧的多个存储单元的第二阵列; 第一行，包括布置在第一侧的多个中点参考单元; 以及第二排，包括布置在第二侧的多个中点参考单元，其中第一行的每个中点参考单元被配置为产生第一参考电压，并且其中第二行的每个中点参考单元 行被配置为产生第二参考电压; 其中所述读出放大器被配置为基于所述第二参考电压来确定所述第一阵列的存储单元的电阻状态; 其中所述读出放大器被配置为基于所述第一参考电压来确定所述第二阵列的存储单元的电阻状态。

公开(公告)号：WO2016048376A1

公开(公告)日：2016-03-31

申请号：PCT/US2014/057865

申请日：2014-09-26

Applicant: INTEL CORPORATION ,  DOCZY, Mark L. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  CHAU, Robert S. ,  SURI, Satyarth

Inventor： DOCZY, Mark L. ,  OGUZ, Kaan ,  DOYLE, Brian S. ,  KUO, Charles C. ,  CHAU, Robert S. ,  SURI, Satyarth

IPC: G11C11/16

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

Abstract translation: 一种用于磁隧道结的材料层堆叠，所述材料层堆叠包括固定的磁性层; 电介质层; 自由磁性层; 和非晶导电种子层，其中固定磁性层设置在电介质层和籽晶层之间。 一种非易失性存储器件，包括：包括非晶导电种子层的材料堆叠; 并且固定的磁性层并置并与种子层接触。 一种方法，包括在存储器件的第一电极上形成无定形晶种层; 在所述非晶种子层上形成材料层堆叠，所述材料堆叠包括设置在固定磁性层和自由磁性层之间的介电层，其中所述固定磁性层。

公开(公告)号：WO2016035758A1

公开(公告)日：2016-03-10

申请号：PCT/JP2015/074735

申请日：2015-08-31

Applicant: 国立研究開発法人理化学研究所

Inventor： 永長　直人 ,  小椎八重　航 ,  岩崎　惇一 ,  川崎　雅司 ,  十倉　好紀 ,  金子　良夫

IPC: H01L29/82 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  G11C11/14 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C19/08 ,  G11C19/0808 ,  G11C19/085 ,  G11C19/0866 ,  H01F7/20 ,  H01F10/3254 ,  H01L27/105 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82 ,  H01L43/06 ,  H01L43/08

Abstract: 　１個のスキルミオンを生成し、１個のスキルミオンの消去が可能な磁気素子であって、略矩形の平板形状の磁性体と、磁性体の幅Ｗｍ方向に接続した非磁性金属からなる上流側電極と、上流側電極と対向して磁性体の幅Ｗｍ方向に接続した非磁性金属からなる下流側電極と、スキルミオンを検出するスキルミオン検出素子とを有し、磁性体の略矩形形状の幅Ｗｍは、スキルミオン直径をλとして、３・λ＞Ｗｍ≧λであり、磁性体の略矩形形状の長さＨｍは、２・λ＞Ｈｍ≧λであり、磁性体は上流側電極および下流側電極が挟む端部に凹部を有する磁気素子を提供する。

Abstract translation: 本发明提供一种能够产生一个电极并消除一个电极的磁性元件，所述磁性元件具有：大致矩形的板状磁性体; 上游电极，其包括非磁性金属，并且以所述磁体的宽度（Wm）方向连接; 包括以磁性体的宽度（Wm）方向连接并与上游电极相对的非磁性金属的下游电极; 以及一个检测爬虫的爬虫检测元件。 当skyrmion的直径定义为λ时，基本矩形磁体的宽度（Wm）为3∙λ

公开(公告)号：WO2015148059A1

公开(公告)日：2015-10-01

申请号：PCT/US2015/018274

申请日：2015-03-02

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Xia ,  LEE, Kangho ,  CHEN, Wei-Chuan ,  LU, Yu ,  PARK, Chando ,  KANG, Seung Hyuk

IPC: H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：WO2015147875A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032240

申请日：2014-03-28

Applicant: INTEL CORPORATION ,  WIEGAND, Christopher, J. ,  RAHMAN, Md Tofizur ,  GOLONZKA, Oleg ,  JAHAGIRDAR, Anant, H. ,  LU, Mengcheng

Inventor： WIEGAND, Christopher, J. ,  RAHMAN, Md Tofizur ,  GOLONZKA, Oleg ,  JAHAGIRDAR, Anant, H. ,  LU, Mengcheng

IPC: G11C11/15

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了通过植入调制磁性能的技术和配置。 在一个实施例中，一种方法包括提供具有设置在基板上的集成电路（IC）结构的基板，该IC结构包括可磁化材料，用掺杂剂注入至少一部分可磁化材料并使可磁化材料磁化，其中 在可磁化材料的注入部分中抑制了磁化。 可以描述和/或要求保护其他实施例。