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    MULTI-CORE MULTI-THREAD PROCESSOR
    1.
    发明申请
    MULTI-CORE MULTI-THREAD PROCESSOR 审中-公开
    多核多线程处理器

    公开(公告)号：WO2005020067A3

    公开(公告)日：2006-05-26

    申请号：PCT/US2004024956

    申请日：2004-07-30

    Applicant: SUN MICROSYSTEMS INC ,  OLUKOTUN KUNLE A

    Inventor： OLUKOTUN KUNLE A

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/315 ,  G06F12/08 ,  G06F15/78

    CPC classification number: G06F9/3834 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30141 ,  G06F9/3828 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3891 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0842 ,  G06F15/167 ,  G06F15/781

    Abstract: A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

    Abstract translation: 提供处理器。 处理器包括至少两个核。 至少两个内核具有第一级缓存，并且是多线程的。 包括交叉开关。 提供了通过横杆与至少两个核心通信的多个高速缓存组存储器。 多个高速缓存组存储器中的每一个与主存储器接口通信。 包括与主存储器接口通信并提供到至少两个核的链接的多个输入/输出接口模块。 链路绕过多个高速缓存组存储器和交叉开关。 被配置为使得至少两个核能够以隐藏由高速缓存访​​问引起的延迟的方式从第一线程切换到第二线程的线程硬件被包括。 包括用于确定何时切换多核多线程环境中的线程的服务器和方法。

    MULTI-CORE MULTI-THREAD PROCESSOR CROSSBAR ARCHITECTURE
    2.
    发明申请
    MULTI-CORE MULTI-THREAD PROCESSOR CROSSBAR ARCHITECTURE 审中-公开
    多核多线程处理器交叉结构

    公开(公告)号：WO2005020066A3

    公开(公告)日：2006-04-06

    申请号：PCT/US2004024726

    申请日：2004-07-30

    Applicant: SUN MICROSYSTEMS INC ,  OLUKOTUN KUNLE A

    Inventor： OLUKOTUN KUNLE A

    IPC: G06F9/38 ,  G06F12/08 ,  G06F13/16 ,  G06F15/78

    CPC classification number: G06F13/1657 ,  G06F12/0811 ,  G06F12/0842

    Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores where each of the processing cores being multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes a centrally located arbiter configured to sort multiple requests received from the plurality of processing cores and the crossbar is defined over the plurality of processing cores. In another embodiment, the processor chip is oriented so that the cache bank memories are defined in the center region. A server is also included.

    Abstract translation: 提供处理器芯片。 处理器芯片包括多个处理核心，其中每个处理核心是多线程的。 多个处理核心位于处理器芯片的中心区域。 包括多个缓存组存储器。 提供了能够实现多个处理核与多个高速缓存组存储器之间的通信的交叉开关。 交叉开关包括中心定位的仲裁器，其被配置为对从多个处理核心接收到的多个请求进行排序，并且在多个处理核心上定义交叉开关。 在另一个实施例中，处理器芯片被定向成使得高速缓存组存储器被定义在中心区域中。 还包括服务器。

    CACHE CROSSBAR ARBITRATION
    3.
    发明申请
    CACHE CROSSBAR ARBITRATION 审中-公开
    CACHE十字架仲裁

    公开(公告)号：WO2005020079A3

    公开(公告)日：2006-01-12

    申请号：PCT/US2004024869

    申请日：2004-07-30

    Applicant: SUN MICROSYSTEMS INC ,  OLUKOTUN KUNLE A

    Inventor： OLUKOTUN KUNLE A

    IPC: G06F9/38 ,  G06F12/08 ,  G06F13/16 ,  G06F13/36

    CPC classification number: G06F13/1657 ,  G06F9/3851 ,  G06F9/3891 ,  G06F12/084 ,  G06F12/0846

    Abstract: A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured. to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.

    Abstract translation: 提供处理器芯片。 处理器芯片包括多个处理核心，其中每个处理核心是多线程的。 多个处理核心位于处理器芯片的中心区域。 包括多个缓存组存储器。 提供了能够实现多个处理核与多个高速缓存组存储器之间的通信的交叉开关。 交叉开关包括配置的仲裁器。 以可用的输出来仲裁从多个处理核心接收到的多个请求。 仲裁器包括桶形移位器，其被配置为旋转用于动态优先级的多个请求，以及与每个可用输出相关联的优先级编码器。 每个优先编码器具有被配置为禁用优先编码器输出的逻辑门。 包括在多核多线程处理器内仲裁请求的方法。

    CACHE BANK INTERFACE UNIT
    4.
    发明申请
    CACHE BANK INTERFACE UNIT 审中-公开
    CACHE银行接口单元

    公开(公告)号：WO2005020080A3

    公开(公告)日：2005-10-27

    申请号：PCT/US2004024911

    申请日：2004-07-30

    Applicant: SUN MICROSYSTEMS INC ,  OLUKOTUN KUNLE A

    Inventor： OLUKOTUN KUNLE A

    IPC: G06F9/38 ,  G06F12/08 ,  G06F15/78

    CPC classification number: G06F9/3824 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0859 ,  G06F15/7846

    Abstract: A server including an application processor chip. The application processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. A plurality of cache bank memories is included. Each of the cache bank memories include a tag array region configured to store data associated with each line of the cache bank memories, a data array region configured to store the data of the cache bank memories, an access pipeline configured to handle accesses from the plurality of processing cores, and a miss handling control unit configured to control the sequencing of cache-line transfers between a corresponding cache bank memory and a main memory. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided.

    Abstract translation: 包括应用处理器芯片的服务器。 应用处理器芯片包括多个处理核心，其中每个处理核心是多线程的。 包括多个缓存组存储器。 每个高速缓存组存储器包括被配置为存储与高速缓存组存储器的每一行相关联的数据的标签阵列区域，被配置为存储高速缓存组存储器的数据的数据阵列区域，被配置为处理来自多个 的处理核心，以及未命中处理控制单元，其被配置为控制对应的高速缓存存储器存储器和主存储器之间的高速缓存行传输的排序。 提供了能够实现多个处理核与多个高速缓存组存储器之间的通信的交叉开关。

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