公开(公告)号：WO2018114583A4

公开(公告)日：2018-06-28

申请号：PCT/EP2017/082795

申请日：2017-12-14

Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

公开(公告)号：WO2018114583A1

公开(公告)日：2018-06-28

申请号：PCT/EP2017/082795

申请日：2017-12-14

Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

公开(公告)号：WO2007132266A1

公开(公告)日：2007-11-22

申请号：PCT/GB2007/050255

申请日：2007-05-11

Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  NEVIN, William Andrew ,  HÖLKE, Alexander

Inventor： NEVIN, William Andrew ,  HÖLKE, Alexander

IPC: H01L21/762

CPC classification number: H01L21/76256 ,  H01L21/26506 ,  H01L21/3226

Abstract: A semiconductor product comprises an insulator layer and a SOI (Silicon On Insulator) layer on the insulator layer, wherein the SOI layer contains implanted Germanium (Ge) at or near the interface with the insulator layer so as to form gettering sites. The semiconductor product can be manufactured by ion implanting Germanium (Ge) into silicon material and bonding the silicon material onto a handle so as to form a SOI substrate.

Abstract translation: 半导体产品包括在绝缘体层上的绝缘体层和SOI（绝缘体上硅）层，其中SOI层在与绝缘体层的界面处或附近包含植入的锗（Ge），以形成吸杂位点。 可以通过将锗（Ge）离子注入硅材料中并将硅材料粘合到手柄上以形成SOI衬底来制造半导体产品。