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    ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES
    1.
    发明申请
    ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES 审中-公开

    公开(公告)号：WO2018114583A4

    公开(公告)日：2018-06-28

    申请号：PCT/EP2017/082795

    申请日：2017-12-14

    Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

    Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

    IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

    Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

    ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES
    2.
    发明申请
    ISOLATION STRUCTURE FOR MICRO-TRANSFER-PRINTABLE DEVICES 审中-公开

    公开(公告)号：WO2018114583A1

    公开(公告)日：2018-06-28

    申请号：PCT/EP2017/082795

    申请日：2017-12-14

    Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

    Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

    IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

    Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

    ION SENSITIVE FIELD EFFECT TRANSISTOR
    4.
    发明申请
    ION SENSITIVE FIELD EFFECT TRANSISTOR 审中-公开
    离子敏感场效应晶体管

    公开(公告)号：WO2012152308A1

    公开(公告)日：2012-11-15

    申请号：PCT/EP2011/057359

    申请日：2011-05-06

    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  FANG, Ling Gang ,  KOO, Sang Sool

    Inventor： FANG, Ling Gang ,  KOO, Sang Sool

    IPC: G01N27/414

    CPC classification number: G01N27/4148

    Abstract: A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilising CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.

    Abstract translation: 一种CMOS或双极型离子敏感场效应晶体管（ISFET），其包括用于保持液体的离子敏感凹槽，其中所述凹部至少部分地形成在晶体管的栅极的顶部。 还提供了利用CMOS处理步骤制造I敏感场效应晶体管（ISFET）的方法，所述方法包括形成用于至少部分地保持液晶的离子敏感凹槽至晶体管的栅极的顶部。

    TRANSISTOR
    7.
    发明申请
    TRANSISTOR 审中-公开
    晶体管

    公开(公告)号：WO2009101150A1

    公开(公告)日：2009-08-20

    申请号：PCT/EP2009/051660

    申请日：2009-02-12

    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  HU, Yong Hai ,  KHO, Elizabeth Ching Tee ,  LIU, Zheng Chao ,  PAL, Deb Kumar ,  TIONG, Michael Mee Gouh ,  LIU, Jian ,  KEE, Kia Yaw ,  LAU, William Siang Lim

    Inventor： HU, Yong Hai ,  KHO, Elizabeth Ching Tee ,  LIU, Zheng Chao ,  PAL, Deb Kumar ,  TIONG, Michael Mee Gouh ,  LIU, Jian ,  KEE, Kia Yaw ,  LAU, William Siang Lim

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L29/7834 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7835

    Abstract: A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

    Abstract translation: 一种金属氧化物半导体（MOS）晶体管，包括：源极; 一个门 以及漏极，源极，栅极和漏极位于位于衬底中或衬底上的第一掺杂极性的阱结构中或其上; 其中所述源极和漏极中的至少一个包括第一结构，所述第一结构包括：形成第一漂移区的第一区，所述第一区具有与所述第一掺杂极性相反的第二掺杂极性; 所述第二区域是所述第二区域中的第二掺杂极性的第二区域，所述第二区域是阱区并具有高于所述第一区域的掺杂浓度的掺杂浓度; 以及在第二区域中或第二区域上的第二掺杂极性的第三区域。 由于存在第二区域，与不具有第二区域的类似晶体管相比，晶体管可能具有较低的导通电阻。 击穿电压可能仅在很小程度上受到影响。

    MIS FIELD-EFFECT TRANSISTOR
    8.
    发明申请
    MIS FIELD-EFFECT TRANSISTOR 审中-公开
    MIS场效应晶体管

    公开(公告)号：WO2009013537A1

    公开(公告)日：2009-01-29

    申请号：PCT/GB2008/050606

    申请日：2008-07-21

    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  STRIBLEY, Paul, Ronald

    Inventor： STRIBLEY, Paul, Ronald

    IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

    CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368

    Abstract: A transistor comprising a source region, a gate (10), a drain region (13), a gate dielectric layer (11, 12) for isolating the gate from an underlying body (14, 6), and a well region (5) at least partially extending under the gate to create a channel region, wherein the gate dielectric layer comprises a thinner portion (12) and a thicker portion (11), and wherein the thickness of the thicker portion is no more than 200nm.

    Abstract translation: 一种晶体管，包括源极区，栅极（10），漏极区（13），用于将栅极与下面的本体（14,6）隔离的栅极电介质层（11,12）和阱区（5） 至少部分地在所述栅极下方延伸以产生沟道区，其中所述栅介质层包括较薄部分（12）和较厚部分（11），并且其中较厚部分的厚度不大于200nm。

    MIM CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    MIM CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING THE SAME 审中-公开
    MIM电容器结构及其制造方法

    公开(公告)号：WO2009013533A1

    公开(公告)日：2009-01-29

    申请号：PCT/GB2008/050600

    申请日：2008-07-18

    Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  STRIBLEY, Paul, Ronald ,  PARSONS, Mark ,  CHAPMAN, Graham

    Inventor： STRIBLEY, Paul, Ronald ,  PARSONS, Mark ,  CHAPMAN, Graham

    IPC: H01L21/02 ,  H01G4/33

    CPC classification number: H01G4/33 ,  H01L28/40

    Abstract: A device comprises a substrate (22); a first MiM capacitor (10, 20, 11) disposed over the substrate; and a second MiM capacitor (10', 20', 11') disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (10, 10') of the CMOS process as one plate and a thinner conductive layer (11, 11') as the second plate, with an insulating layer (20, 20') disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimises the number of masks required, and so minimises the mask investment cost.

    Abstract translation: 一种器件包括衬底（22）; 设置在所述衬底上的第一MiM电容器（10,20,11） 以及设置在所述第一MiM电容器上的第二MiM电容器（10'，20'，11'）。 第一个MiM电容器和第二个MiM电容器并联电连接。 两个MiM电容器垂直堆叠在一起。 每个MiM电容器包括作为一个板的CMOS工艺的互连层（10,10'）和作为第二板的较薄的导电层（11,11'），其间设置绝缘层（20,20'）。 这允许在两个CMOS工艺互连层之间形成每个MiM电容器。 第二MiM电容器的第二板与第一MiM电容器的第二板基本上共同扩展，并且基本上直接布置在第一MiM电容器的第二板上。 可以使用相同的掩模来图案化第二MiM电容器的第二板和第一MiM电容器的第二板。 这最大限度地减少了掩模所需的数量，从而最小化掩模投资成本。

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