公开(公告)号：WO2018114583A4

公开(公告)日：2018-06-28

申请号：PCT/EP2017/082795

申请日：2017-12-14

Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

公开(公告)号：WO2018114583A1

公开(公告)日：2018-06-28

申请号：PCT/EP2017/082795

申请日：2017-12-14

Applicant: X-CELEPRINT LIMITED ,  X-FAB SEMICONDUCTOR FOUNDRIES AG

Inventor： BOWER, Christopher Andrew ,  COK, Ronald S. ,  NEVIN, William Andrew ,  KITTLER, Gabriel

IPC: H01L21/84 ,  H01L21/683 ,  H01L25/00

Abstract: A semiconductor structure suitable for micro-transfer printing comprises a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. In some embodiments, each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. In some embodiments, the etch via is empty and the semiconductor substrate is patterned to forma gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor (e.g., a portion of the semiconductor substrate or the patterned insulation layer).

公开(公告)号：WO2011051499A1

公开(公告)日：2011-05-05

申请号：PCT/EP2010/066642

申请日：2010-11-02

Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  KITTLER, Gabriel ,  LERNER, Ralf

Inventor： KITTLER, Gabriel ,  LERNER, Ralf

IPC: H01L21/02

CPC classification number: H01L21/02538 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02639 ,  H01L21/76283

Abstract: Es wird ein Verfahren zur Herstellung von Siliziumhalbleiterscheiben und Bauelementen mit Schichtstrukturen von Ill-V-Schichten zur Integration von IIl-V Halbleiterbauelementen beschrieben. Es werden SOI-Silizium-Halbleiterscheiben mit unterschiedlicher Substratorientierung eingesetzt, und die III-V-Halbleiterschichten werden in durch Ätzen erzeugten Gruben (28, 43, 70) innerhalb von bestimmten, elektrisch voneinander isolierten Bereichen (38, 39) der aktiven Halbleiterschicht (24, 42) mittels Abdeckschicht(en) (29) unter Einsatz von MOCVD-Verfahren erzeugt.

Abstract translation: 提供了一种用于制造硅晶片和具有用于集成所述的IIL-V族半导体器件的III-V层的层结构的器件的方法。 SOI硅晶片与不同的基片的取向使用，并且III-V族半导体层是通过蚀刻有源半导体层的某些电隔离区中的凹坑（28，43，70）（38,39）中产生（24 采用MOCVD法，42）（通过覆盖S的装置）中产生（29）。

公开(公告)号：WO2011098866A1

公开(公告)日：2011-08-18

申请号：PCT/IB2010/050676

申请日：2010-02-15

Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  TEXAS INSTRUMENTS INCORPORATED ,  LERNER, Ralf ,  HOWER, Phil ,  KITTLER, Gabriel ,  SCHOTTMANN, Klaus

Inventor： LERNER, Ralf ,  HOWER, Phil ,  KITTLER, Gabriel ,  SCHOTTMANN, Klaus

IPC: H01L21/335

CPC classification number: H01L29/7828 ,  H01L29/0623 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666

Abstract: A depletion type DMOS transistor comprises a gap in electrode material allowing incorporation of a well dopant species into the underlying semiconductor material. During subsequent dopant diffusion a continuous well region is obtained having an extended lateral extension without having an increased depth. The source dopant species is implanted after masking the gap. Additional channel implantation is performed prior to forming the gate dielectric material.

Abstract translation: 耗尽型DMOS晶体管包括电极材料中的间隙，允许将阱掺杂剂物质结合到下面的半导体材料中。 在随后的掺杂剂扩散期间，获得具有延伸的横向延伸而不增加深度的连续井区。 在掩盖间隙之后植入源掺杂剂物质。 在形成栅极电介质材料之前执行附加沟道注入。

公开(公告)号：WO2011051500A1

公开(公告)日：2011-05-05

申请号：PCT/EP2010/066656

申请日：2010-11-02

Applicant: X-FAB SEMICONDUCTOR FOUNDRIES AG ,  KITTLER, Gabriel ,  LERNER, Ralf

Inventor： KITTLER, Gabriel ,  LERNER, Ralf

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/20 ,  H01L21/205

CPC classification number: H01L21/8258 ,  H01L21/8252 ,  H01L21/84 ,  H01L27/0605 ,  H01L27/1203

Abstract: Es wird ein Verfahren zur Herstellung von Siliziumhalbleiterscheiben mit Schichtstrukturen von III-V-Halbleiterschichten zur Integration von auf III-V-Halbleiterschichten basierenden HEMTs mit Silizium-Bauelementen beschrieben. SOI-Silizium-Halbleiterscheiben werden eingesetzt, auf deren aktiven Halbleiterschicht die III-V-Halbleiterschichten (24) des HEMT-Aufbaus (2) über zwei voneinander isolierte Bereiche (24a, 24b) der aktiven Siliziumschicht reichend platziert werden. Eine entsprechende Schichtanordnung ist ebenfalls offenbart.

Abstract translation: 提供了一种用于制造具有III-V族半导体层的多层结构为一体基于III-V半导体层的HEMT的与所描述的硅成分的硅半导体晶片的方法。 SOI硅晶片中使用的，有源半导体层上，通过两个相互绝缘的区域中的HEMT结构（2）的III-V族半导体层（24）（24A，24B）被放置在有源硅层达到。 相应层排列也被公开。