公开(公告)号：WO1996001474A1

公开(公告)日：1996-01-18

申请号：PCT/US1995008497

申请日：1995-07-05

Applicant: ZYCAD CORPORATION

Inventor： ZYCAD CORPORATION ,  LIPP, Robert, J.

IPC: G11C11/34

CPC classification number: G11C16/3427 ,  G11C16/3418

Abstract: A novel method of connecting and operating an NVM transistor (13, 15, 17, 19, 21) in the switching circuit is provided. A full voltage signal can be switched across an NVM transistor. The device is turned on prior to the signal switching and the electrical characteristics of the NVM device relative to the associated circuitry is carefully regulated to prevent the source-drain voltage from rising above a preselected maximum voltage (e.g. 1v). Two embodiments of the present invention are described. In the first embodiment, the relative impedances of the NVM transistor and its driving circuit are controlled. The driver circuit and the NVM transistor switch act as a resistor divider circuit with a percentage of the full switching voltage appearing across the NVM transistor and the driver circuit according to their relative impedances. The second embodiment is applicable when the NVM transistor switch drives a capacitive load (40).

Abstract translation: 提供了一种在开关电路中连接和操作NVM晶体管（13,15,17,19,21）的新颖方法。 可以在NVM晶体管上切换全电压信号。 该器件在信号切换之前被接通，并且NVM器件相对于相关电路的电特性被小心地调节以防止源极 - 漏极电压升高到高于预选的最大电压（例如1v）。 对本发明的两个实施例进行说明。 在第一实施例中，控制NVM晶体管及其驱动电路的相对阻抗。 驱动电路和NVM晶体管开关作为电阻分压电路，其全开关电压的百分比根据其相对阻抗出现在NVM晶体管和驱动电路两端。 当NVM晶体管开关驱动电容性负载（40）时，第二实施例是适用的。

公开(公告)号：WO1996001499A1

公开(公告)日：1996-01-18

申请号：PCT/US1995008500

申请日：1995-07-05

Applicant: ZYCAD CORPORATION

Inventor： ZYCAD CORPORATION ,  LIPP, Robert, J. ,  FREEMAN, Richard, D. ,  BROZE, Robert, U. ,  CAYWOOD, John, M. ,  NOLAN, Joseph, G., III

IPC: H01L29/788

CPC classification number: H03K19/1736 ,  G11C16/0441

Abstract: A programmable interconnect which closely integrates an independent switching transistor (40) with separate NVM programming and erasing elements. The programming element is an EPROM transistor (32), and the erasing element is a Fowler-Nordheim tunneling device (31). A unitary floating gate (28) is shared by the switching transistor, the NVM programming elements and the erasing elements. The shared floating gate structure (28) is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor (40).

Abstract translation: 一个可编程互连，将独立的开关晶体管（40）与独立的NVM编程和擦除元件紧密集成。 编程元件是EPROM晶体管（32），擦除元件是Fowler-Nordheim隧穿装置（31）。 一个单一的浮动栅极（28）由开关晶体管，NVM编程元件和擦除元件共享。 共享浮栅结构（28）是集成可编程互连的存储结构，并控制开关晶体管（40）的阻抗。

公开(公告)号：WO1994022142A1

公开(公告)日：1994-09-29

申请号：PCT/US1994002885

申请日：1994-03-16

Applicant: ZYCAD CORPORATION

Inventor： ZYCAD CORPORATION ,  FREEMAN, Richard, D.

IPC: G11C11/403

CPC classification number: H03K19/177 ,  G11C7/1006 ,  G11C11/406 ,  H03K19/17704

Abstract: A field programmable device includes two separate and electrically isolated arrays (11 and 60) of rows and columns of conductors sharing the same area of an integrated circuit substrate, one array (11) interconnecting memory cells to form a random access memory (78) ("RAM"). The other array (60) forms a full or partial cross-point switching network (65) that is controlled by information stored in memory cells, and/or connects to an operating electronic circuit (66) that is configurable and operable in accordance with information stored in memory cells. In addition, the memory array (11) is easily used to access desired modes of the circuit array (60) in order to be able to easily observe internal signals during operation. A preferred memory structure is a dynamic random access memory ("DRAM") because of a high density and low cost of existing DRAM fabrication techniques, even though periodic reading and refreshing of the states of the memory cells is required. Several circuits (21, 25 and 41) and techniques are used which allow continuous assertion of the memory cell states without interruption during their refreshing cycles.

Abstract translation: 现场可编程器件包括两个独立且电隔离的阵列（11和60），这些阵列和列分别具有集成电路衬底的相同区域，一个阵列（11）互连存储器单元以形成随机存取存储器（78）（ “随机存取存储器”）。 另一个阵列（60）形成由存储在存储器单元中的信息控制的全部或部分交叉点交换网络（65）和/或连接到可根据信息配置和操作的操作电子电路（66） 存储在存储单元中。 此外，存储器阵列（11）容易地用于访问电路阵列（60）的期望模式，以便能够在操作期间容易地观察内部信号。 优选的存储器结构是动态随机存取存储器（“DRAM”），因为即使需要定期读取和刷新存储器单元的状态，因为现有DRAM制造技术的高密度和低成本。 使用几个电路（21,25和41）和技术，其允许在其刷新周期期间不间断地连续断言存储器单元状态。

公开(公告)号：WO1997005662A1

公开(公告)日：1997-02-13

申请号：PCT/US1996011219

申请日：1996-07-01

Applicant: ZYCAD CORPORATION

Inventor： ZYCAD CORPORATION ,  BROZE, Robert, U.

IPC: H01L29/788

CPC classification number: H01L27/11517 ,  H01L27/115 ,  H01L29/7883

Abstract: An array of programmable interconnect cells, each cell having a floating gate as the gate of an MOS switch transistor which programmably connects or disconnects nodes, is used in an FPGA. The floating gate (15G) of each cell, which is capacitively coupled to a control gate (53), is programmed by Fowler-Nordheim tunneling through an tunneling oxide (31G) above a programming/erase line (41) in the integrated circuit substrate (40). Contiguous and parallel to the programming/erase line is at least one tunneling control line (71A, B) which forms a PN junction in close proximity to the programming/erase line region under the tunneling oxide. Under reverse bias, a deep charge depletion region is formed in the programming/erase line region to block tunneling. In this manner, a selected cell can be programmed/erased, while the non-selected cells are not.

Abstract translation: 在FPGA中使用可编程互连单元的阵列，每个单元具有浮动栅极作为可编程地连接或断开节点的MOS开关晶体管的栅极。 电容耦合到控制栅极（53）的每个单元的浮动栅极（15G）通过Fowler-Nordheim隧穿通过集成电路基板中的编程/擦除线（41）上方的隧道氧化物（31G）来编程 （40）。 与编程/擦除线相连和平行的是至少一个隧道化控制线（71A，B），其形成紧邻隧道氧化物下的编程/擦除线区域的PN结。 在反向偏置下，在编程/擦除线区域中形成深电荷耗尽区，以阻止隧穿。 以这种方式，可以对所选择的单元进行编程/擦除，而未选择的单元不被编程。

公开(公告)号：WO1996031950A1

公开(公告)日：1996-10-10

申请号：PCT/US1996003599

申请日：1996-03-14

Applicant: ZYCAD CORPORATION

Inventor： ZYCAD CORPORATION ,  FREEMAN, Richard, D. ,  LINOFF, Joseph, D. ,  SAXE, Timothy

IPC: H03K07/38

CPC classification number: H03K19/17736 ,  H03K19/17704

Abstract: The present invention provides for an FPGA integrated circuit having an array of logic cells (10) and interconnect lines (X1, X2, X3) interconnected by programmable switches (24-29), each formed from a nonvolatile memory cell. The logic cell (10) is designed to provide logic or memory functions according to the setting of programmable switches (30-33) within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between wiring segments.

Abstract translation: 本发明提供了一种FPGA集成电路，其具有由可编程开关（24-29）互连的逻辑单元阵列（10）和互连线（X1，X2，X3），每个由非易失性存储单元形成。 逻辑单元（10）被设计成根据单元内的可编程开关（30-33）的设置来提供逻辑或存储器功能。 阵列中的逻辑单元可通过本地，长整体和全局布线段的层次结构互连。 互连通过布线段之间的可编程开关的设置来实现。