公开(公告)号：WO2019067337A1

公开(公告)日：2019-04-04

申请号：PCT/US2018/052346

申请日：2018-09-24

申请人： KNOWLES ELECTRONICS, LLC

发明人： RUB, Leonardo ,  CLARK, Brian

IPC分类号： G06F15/78

CPC分类号： G06F15/76 ,  G06F15/7817 ,  G06F15/8053

摘要： A multi-core audio processor includes a data protocol interface configured to receive a stream of audio data, a plurality of data processing cores including a single sample processing core and a block data processing core, an audio fabric block configured to route samples of the stream between the data protocol interface and the plurality of data processing cores. The single sample processing core includes an execution unit configured to execute one or more low latency instructions for performing computations for the samples.

公开(公告)号：WO2018212711A1

公开(公告)日：2018-11-22

申请号：PCT/SG2018/050234

申请日：2018-05-15

申请人： NATIONAL UNIVERSITY OF SINGAPORE

发明人： HE, Xiangnan ,  CHUA, Tat-Seng

IPC分类号： G06N3/02 ,  G06F15/18 ,  G06N7/00

CPC分类号： G06F15/76 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/082

摘要： Methods and systems for predictive analysis are disclosed, A predictive analysis method comprises: receiving a set of predictor variables as an input feature vector comprising a plurality of features; projecting each feature of the feature vector onto a dense vector representation to obtain a set of embedding vectors representing the input feature vector in an embedding space; converting the set of embedding vectors into a bi-interaction pooling vector that encodes second-order interactions between features of the feature vector in the embedding space; inputting the bi-interaction pooling vector into a hidden layer stack, the hidden layer stack comprising at least one hidden layer of neural network nodes; and transforming an output vector of the hidden layer stack into a prediction score.

公开(公告)号：WO2018164762A1

公开(公告)日：2018-09-13

申请号：PCT/US2018/012077

申请日：2018-01-02

申请人： QUALCOMM INCORPORATED

发明人： SAMADI, Kambiz ,  ANSARI, Amin ,  DU, Yang

IPC分类号： G06F15/76 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06

CPC分类号： G06F15/80 ,  G06F9/3012 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3867 ,  G06F12/0875 ,  G06F15/76 ,  G06F15/803 ,  G06F2212/452 ,  H01L21/8221 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541

摘要： Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores ("cores") to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：WO2018150316A1

公开(公告)日：2018-08-23

申请号：PCT/IB2018/050861

申请日：2018-02-13

申请人： GUPTA, Shally Vijayendra

发明人： GUPTA, Shally Vijayendra ,  ANAND, Ashish ,  GUPTA, Vijayendra Kumar

IPC分类号： G06F15/16 ,  G06F17/30 ,  H04L12/911

CPC分类号： G06F15/76 ,  G06F15/16

摘要： A computational resource network to prioritize nodes in a network. A computational resource network (100) comprises a plurality of nodes (A-N) and at least one database (104). The nodes (A-N) are interconnected to form the network (102). Each of the nodes (A-N) is configured to receive resource from at least one other node (A-N) in the network (102) or share resource with at least one other node (A-N) in the network (102). The database (104) records, for each of the nodes (A-N), information corresponding to resources received from and shared with other nodes in the network (102) and prioritises nodes (A-N) in the network (102) at least based on said information associated with each of the nodes (A-N) corresponding to the resources received from and shared with other nodes (A-N) in the network (102).

公开(公告)号：WO2018136534A1

公开(公告)日：2018-07-26

申请号：PCT/US2018/014078

申请日：2018-01-17

申请人： FAIR IP, LLC

发明人： PAINTER, Scott Edward ,  MADENIAN, Serge ,  NGUYEN, David Luan ,  NAUGHTON, Ryan James ,  ASHPIS, Gilad

IPC分类号： G06Q40/02 ,  G06Q40/00 ,  G06F9/44 ,  G06F17/50

CPC分类号： G06Q40/025 ,  G06F15/76 ,  G06F16/252 ,  G06N20/00 ,  G06Q40/08

摘要： A rules/model-based data processing system that approves applications by users of the data processing system based on data from distributed sources. The system is configured to receive a request to approve a user application, access rules/models that fit the goal of approving the user application, obtain data from distributed sources, apply rules/models to generate processed data and determines if the obtained or processed data fits the rules. The system comprises a server configured to access the approval rules based on a request from a mobile application to approve the user application, the approval rules referencing information provider data from a remote information provider system. The server can connect to the remote information provider system to retrieve, using personally identifiable information from the user application, the set of information provider data referenced and approve the user application based on the application of the approval rules to the information provider data.

公开(公告)号：WO2018125437A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/062677

申请日：2017-11-21

申请人： INTEL CORPORATION

发明人： BANDI, Chenchu Punnarao Rao ,  SRIVASTAVA, Amit Kumar

IPC分类号： H04L25/08 ,  H04L25/03 ,  H04B3/32

CPC分类号： G06F13/4022 ,  G06F13/4282 ,  G06F15/76 ,  G06F15/7807

摘要： Aspects of the embodiments are directed to calibrating a cross-talk cancellation module. A data eye response for a first data channel can be acquired, and the left-side and right-side maximum transition edges can be determined while adjacent data channels are silent. The adjacent data channels can be activated, first using an even mode waveform. A strobe can be positioned at the left-side maximum boundary in anticipation of a right-shift due to even mode waveform cross talk. A summer circuit can sum the waveform from the first data channel with cross-talk induced voltage pulse having an opposite polarity from the even mode waveforms on the aggressor channels. A left-side edge can be determined by incrementally adjusting gain and detector parameters. These parameters can be locked once a left-side transition edge is located. The process can be repeated for a right-side transition edge with odd-mode aggressor waveforms.

公开(公告)号：WO2018125409A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/061713

申请日：2017-11-15

申请人： INTEL CORPORATION

发明人： IDO, Hideki Saito ,  GARCIA, Eric N. ,  TIAN, Xinmin ,  GIRKAR, Milind B. ,  BRODMAN, James

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/30058 ,  G06F9/3806 ,  G06F15/76

摘要： In one example, a system for generating vector based selection control statements can include a processor to determine a vector cost of the selection control statement is below a scalar cost and determine the selection control statement is to be executed in a sorted order based on dependencies between branch instructions of the selection control statement. The processor can also determine a program ordering of labels of the selection control statement does not match a mathematical ordering of the labels and execute the selection control statement with a vector of values, wherein the selection control statement is to be executed based on a jump table and a sorted unique value technique, wherein the sorted unique value technique comprises selecting at least one of the plurality of branch instructions from the jump table.

公开(公告)号：WO2017067402A1

公开(公告)日：2017-04-27

申请号：PCT/CN2016/101735

申请日：2016-10-11

申请人： 阿里巴巴集团控股有限公司

发明人： 牛功彪 ,  李舒

IPC分类号： G06F15/76

CPC分类号： G06F15/76

摘要： 一种计算设备及计算设备存储部件的管理方法及系统，所述计算设备包括：计算部件（20），还包括：与SAS SWITCH连接的接口（21）；所述计算部件（20）通过所述接口（21）与SAS SWITCH连接，所述SAS SWITCH同时与存储部件连接；基于分配规则为连接于SAS SWITCH上的所述计算部件（20）分配存储部件。实现了计算部件和存储部件的生命周期分开，便于对不同生命周期的部件进行最大限度的利用，以及实现了计算部件与存储部件的解耦，计算部件与存储部件可以精细化、灵活分配。

公开(公告)号：WO2017033112A1

公开(公告)日：2017-03-02

申请号：PCT/IB2016/054987

申请日：2016-08-19

申请人： PATEL, Sureshchandra

发明人： PATEL, Sureshchandra

IPC分类号： G06F15/76 ,  G06F1/16 ,  G06F15/16

CPC分类号： G06F1/20 ,  G06F1/1656 ,  G06F1/1698 ,  G06F15/16 ,  G06F15/76

摘要： A fan less Multiprocessor Computing Apparatus (MCA) is housed in a metallic Enclosure (ME) that acts as a heat sink and provides extended surface area for heat dissipation. The ME also acts as an electro-magnetic-Shield that provides immunity from Electro-Magnetic-Interference from external stray magnetic fields to wireless communications among components of MCA. The Wireless Interconnect involving Transceiver Antenna can use whole range of radio, microwave, and optical frequencies involving transceivers and antennas. Printed Circuit Boards of MCA are mounted on inside of metallic surfaces of ME of any required size and shape. MEs are filled with vacuum or clean dust free air without any suspended particles for efficient and reliable communications. Electro-magnetically shielded and sealed MEs housing MCAs are made dust and water proof so that they can be placed under water in a sea or a river, particularly MCAs constituting large data/cloud centres. Also, Shared Memory Units are made up of non-volatile static Magneto-Optical or Optical recordable, erasable, and recordable media in square/rectangular form factor.

摘要翻译： 多风扇多处理器计算设备（MCA）安装在金属外壳（ME）中，作为散热器，并提供扩展的表面积进行散热。 ME还作为一种电磁屏蔽，可以将电磁干扰从外部杂散磁场提供给MCA组件之间的无线通信。 涉及收发天线的无线互连可以使用涉及收发器和天线的全系列无线电，微波和光频。 MCA的印刷电路板安装在任何所需尺寸和形状的ME的金属表面的内部。 充满真空或清洁无尘的空气，无任何悬浮颗粒，以实现有效和可靠的通讯。 电磁屏蔽和密封的MEs住房MCAs被制成防尘和防水的，以便它们可以放置在海洋或河流中的水下，特别是构成大型数据/云中心的MCA。 此外，共享存储单元由非易失性静态磁光或光可记录，可擦除和可记录的介质组成，方形/矩形形状。

公开(公告)号：WO2017024371A1

公开(公告)日：2017-02-16

申请号：PCT/BR2016/050189

申请日：2016-08-11

申请人： UNIAO BRASILEIRA DE EDUCACAO E ASSISTENCIA

发明人： VARGAS, Fabian Luis ,  GREEN, Bruno Naspolini

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F9/46 ,  G06F9/44 ,  G06F9/00 ,  G06F11/00 ,  G06F15/76

CPC分类号： G06F9/00 ,  G06F9/44 ,  G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F11/00 ,  G06F15/76

摘要： A presente invenção descreve um processo de determinação exata do tempo máximo de execução da tarefa crítica de um sistema embarcado baseado em um processador multicore . Para tanto, propõe-se a utilização de um hardware específico cuja função é analisar e controlar o tempo de execução da referida tarefa. Especificamente, o objetivo do sistema é garantir que o tempo de resposta máximo da função crítica do programa executado pelo processador não exceda um limite pré-definido, e, caso essa tarefa crítica não seja encerrada até o limite, o sistema desabilita os demais núcleos do processador, mantendo em operação apenas o núcleo que está executando a tarefa crítica. O hardware específico, implementado por um sistema com watchdog , é configurado com informação pertinente à execução do programa crítico de forma isolada (isto é, em um processador com um único núcleo), o que é de complexidade computacional limitada e extremamente factível, e que monitora o tempo de execução da referida tarefa sem a necessidade de saber qual é o valor do tempo máximo de execução para este programa em um ambiente com vários núcleos de um microprocessador. A presente invenção se situa nos campos da Eletrônica e da Computação.

摘要翻译： 本发明描述了一种用于精确地确定基于多核处理器的嵌入式系统的关键任务的最大执行时间的方法。 为此，提出了使用特定的硬件，具有分析和定时执行任务的功能。 更具体地说，系统的目的是确保由处理器执行的程序的关键功能的最大响应时间不超过预设限制，并且如果该关键任务在该限制之前未完成，则系统禁用 其他处理器内核，只保留正在执行关键任务的核心。 使用看门狗系统实现的特定硬件配置有与执行关键程序相关的信息（也就是说，在具有单个内核的处理器中），具有降低的计算复杂性和极端可行性，监视 任务的执行时间，而不需要知道在具有多个微处理器内核的环境中该程序的执行时间的最大值是多少。 本发明涉及电子学和计算机科学领域。