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    APPARATUS AND METHOD FOR MULTI-LEVEL CACHE REQUEST TRACKING
    1.
    发明申请
    APPARATUS AND METHOD FOR MULTI-LEVEL CACHE REQUEST TRACKING 审中-公开

    公开(公告)号：WO2019067115A1

    公开(公告)日：2019-04-04

    申请号：PCT/US2018/047647

    申请日：2018-08-23

    Applicant: INTEL CORPORATION

    Inventor： BLANKENSHIP, Robert G. ,  SURY, Samantika S.

    IPC: G06F12/0811 ,  G06F12/0888 ,  G06F12/0897

    Abstract: An apparatus and method for multi-level cache request tracking. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; a memory subsystem comprising a system memory and a multi-level cache hierarchy; a primary tracker to store a first entry associated with a memory request to transfer a cache line from the system memory or a first cache within the cache hierarchy to a second cache; primary tracker allocation circuitry to allocate and deallocate entries within the primary tracker; a secondary tracker to store a second entry associated with the memory request; secondary tracker allocation circuitry to allocate and deallocate entries within the secondary tracker; the primary tracker allocation circuitry to deallocate the first entry in response to a first indication that one or more cache coherence requirements associated with the cache line have been resolved, the secondary tracker allocation circuitry to deallocate the second entry in response to a second indication related to transmission of the cache line to the second cache.

    SHARING AWARE SNOOP FILTER APPARATUS AND METHOD
    2.
    发明申请
    SHARING AWARE SNOOP FILTER APPARATUS AND METHOD 审中-公开
    共享史努比滤波器装置和方法

    公开(公告)号：WO2017172296A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/021093

    申请日：2017-03-07

    Applicant: INTEL CORPORATION

    Inventor： SURY, Samantika S. ,  BLANKENSHIP, Robert G. ,  STEELY JR, Simon C.

    IPC: G06F12/0831 ,  G06F12/0811

    Abstract: An apparatus and method are described for a sharing aware snoop filter. For example, one embodiment of a processor comprises: a plurality of caches, each of the caches comprising a plurality of cache lines, at least some of which are to be shared by two or more of the caches; a snoop filter to monitor accesses to the plurality of cache lines shared by the two or more caches, the snoop filter comprising: a primary snoop filter comprising a first plurality of entries, each entry associated with one of the plurality of cache lines and comprising a N unique identifiers to uniquely identify up to N of the plurality of caches currently storing the cache line; an auxiliary snoop filter comprising a second plurality of entries, each entry associated with one of the plurality of cache lines, wherein once a particular cache line has been shared by more than N caches, an entry for that cache line is allocated in the auxiliary snoop filter to uniquely identify one or more additional caches storing the cache line.

    Abstract translation: 针对共享感知窥探过滤器描述了一种设备和方法。 例如，处理器的一个实施例包括：多个高速缓存，每个高速缓存包括多个高速缓存线，其中至少一些高速缓存线由两个或更多个高速缓存共享; 窥探过滤器，用于监视对由所述两个或更多个高速缓存共享的所述多个高速缓存行的访问，所述探听过滤器包括：主窥探过滤器，包括第一多个条目，每个条目与所述多个高速缓存行中的一个相关联并且包括 N个唯一标识符，用于唯一标识当前存储高速缓存行的多个高速缓存中的N个; 包括第二多个条目的辅助侦听过滤器，每个条目与所述多个高速缓存行中的一个相关联，其中一旦特定高速缓存行已被多于N个高速缓存共享，则用于该高速缓存行的条目被分配到所述辅助监听 过滤器来唯一标识一个或多个存储缓存行的附加缓存。

    SYSTEMS, METHODS, AND APPARATUSES FOR RANGE PROTECTION
    3.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR RANGE PROTECTION 审中-公开

    公开(公告)号：WO2017117321A3

    公开(公告)日：2017-07-06

    申请号：PCT/US2016/069066

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： GUIM BERNAT, Francesc ,  KUMAR, Karthik ,  WILLHALM, Thomas ,  RAMANUJAN, Raj K. ,  BLANKENSHIP, Robert G.

    IPC: G06F12/02 ,  G06F9/30

    Abstract: Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

    MULTICHIP PACKAGE LINK ERROR DETECTION
    4.
    发明申请
    MULTICHIP PACKAGE LINK ERROR DETECTION 审中-公开
    多媒体封装链路错误检测

    公开(公告)号：WO2017052661A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2015/052509

    申请日：2015-09-26

    Applicant: INTEL CORPORATION

    Inventor： IYER, Venkatraman ,  BLANKENSHIP, Robert G. ,  WAGH, Mahesh ,  WU, Zuoguo

    IPC: H04L1/00 ,  H04L1/20 ,  H04L29/06

    CPC classification number: G06F11/1004 ,  G06F13/16 ,  G06F2213/16 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0075 ,  H04L1/1607 ,  H04L1/20 ,  H04L29/06 ,  H04L2001/0094

    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    Abstract translation: 在物理链路的多个数据通道上接收第一数据，并且在标识第一数据的类型的流道上接收与第一数据相对应的流信号。 在第一数据中识别特定类型的错误检测码的第一实例。 在多个数据通道的至少一部分上接收第二数据，并且在标识第二数据的类型的流线路上接收对应于第二数据的流信号。 在第二数据中识别特定类型的错误检测码的第二实例。 流道是物理链路的另一条通道，在某些情况下，第二数据的类型与第一数据的类型不同。

    METHOD, APPARATUS, AND SYSTEM FOR CACHE COHERENCY USING A COARSE DIRECTORY
    6.
    发明申请
    METHOD, APPARATUS, AND SYSTEM FOR CACHE COHERENCY USING A COARSE DIRECTORY 审中-公开
    用于使用粗略目录的高速缓存一致性的方法，装置和系统

    公开(公告)号：WO2017210143A1

    公开(公告)日：2017-12-07

    申请号：PCT/US2017/034889

    申请日：2017-05-28

    Applicant: INTEL CORPORATION

    Inventor： BLANKENSHIP, Robert G. ,  STEELY, Simon C. ,  SURY, Samantika S.

    IPC: G06F12/02

    CPC classification number: G06F3/0605 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0824 ,  G06F12/0826 ,  G06F12/0831 ,  G06F12/0842 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13

    Abstract: Systems, methods, and apparatuses are directed to requesting access to a memory address; storing an identification of the memory address in a data structure; receiving a first request for access to the memory address, the request comprising a reference to a second processor core; storing the reference to the second processor in the data structure; receiving a second request for access to the memory address, the second request comprising a reference to a third processor core; determining, based on the data structure, that the third processor core is different from the second processor core; and responding to the second request without buffering the second request.

    Abstract translation: 系统，方法和设备涉及请求访问存储器地址; 将存储器地址的标识存储在数据结构中; 接收访问所述存储器地址的第一请求，所述请求包括对第二处理器核心的引用; 将对第二处理器的引用存储在数据结构中; 接收访问所述存储器地址的第二请求，所述第二请求包括对第三处理器核心的引用; 基于所述数据结构确定所述第三处理器核不同于所述第二处理器核; 并在不缓冲第二个请求的情况下响应第二个请求。

    SYSTEMS, METHODS, AND APPARATUSES FOR RANGE PROTECTION
    7.
    发明申请
    SYSTEMS, METHODS, AND APPARATUSES FOR RANGE PROTECTION 审中-公开
    用于范围保护的系统，方法和装置

    公开(公告)号：WO2017117321A2

    公开(公告)日：2017-07-06

    申请号：PCT/US2016/069066

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： GUIM BERNAT, Francesc ,  KUMAR, Karthik ,  WILLHALM, Thomas ,  RAMANUJAN, Raj K. ,  BLANKENSHIP, Robert G.

    CPC classification number: H04L67/1097 ,  G06F3/0605 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F9/467 ,  H04L67/2809 ,  H04L69/12

    Abstract: Systems, methods, and apparatuses for range protection. In some embodiments, an apparatus comprises at least one monitoring circuit to monitor for memory accesses to an address space and take action upon a violation to the address space, wherein the action is one of generating a notification to a node that requested the monitor, generating the wrong request, generate a notification in a specific context of the home node, and generating a notification in a node that has ownership of the address space; at least one a protection table to store an identifier of the address space; and at least one hardware core to execute an instruction to enable the monitoring circuit.

    Abstract translation: 用于范围保护的系统，方法和装置

    。 在一些实施例中，一种装置包括至少一个监视电路，用于监视对地址空间的存储器访问并且在违反地址空间时采取动作，其中所述动作是向请求监视器的节点生成通知， 错误请求，在主节点的特定上下文中生成通知，并且在具有地址空间所有权的节点中生成通知; 至少一个保护表，用于存储地址空间的标识符; 和至少一个硬件核心来执行指令来启用监视电路。

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