公开(公告)号：WO2017219463A1

公开(公告)日：2017-12-28

申请号：PCT/CN2016/094913

申请日：2016-08-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre ,  WONG, Henry ,  TONIETTO, Davide

IPC: H03M1/10

Abstract: A system, circuit, and method for correcting clock skew in time-interleaved analog-to-digital converters. At least two clock signals are received along respective channels(902). A delay of a first channel, carrying a first clock signal, is accounted for by applying one or more first adjustment factors to the channels until an edge of the first clock signal is aligned with a transition point of a reference signal. The first clock signal is swapped to the second channel(904), and vice-versa. A value of the reference signal as sampled by the first clock signal is compared to values of the reference signal as sampled by the second clock signal to determine a skew of the second channel vis-à-vis the first channel(906), and one or more second adjustment factors are applied to the second channel based on the determined skew of the second channel(908).

Abstract translation: 用于校正时间交织的模数转换器中的时钟偏差的系统，电路和方法。 沿着相应的通道接收至少两个时钟信号（902）。 承载第一时钟信号的第一信道的延迟通过向信道应用一个或多个第一调整因子来解决，直到第一时钟信号的边缘与参考信号的转变点对齐为止。 第一时钟信号被交换到第二信道（904），反之亦然。 将由第一时钟信号采样的参考信号的值与由第二时钟信号采样的参考信号的值进行比较，以确定第二信道相对于第一信道（906）的偏斜，以及 基于所确定的第二信道的偏斜，将一个或多个第二调整因子应用于第二信道（908）。

公开(公告)号：WO2016134604A1

公开(公告)日：2016-09-01

申请号：PCT/CN2015/096818

申请日：2015-12-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H03F3/193 ,  H03F3/45197 ,  H03F2203/45112 ,  H03F2203/45222 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03G5/14

Abstract: A transadmittance amplifier stage is coupled to a transimpedance amplifier stage to form a continuous time linear equalizer. The transadmittance amplifier stage has first and second gain paths and is configured to input a first signal and output a second signal. The first gain path is configured to provide a DC gain recovery and a first high frequency gain to the first signal. The second gain path is configured to provide a second high frequency gain to the first signal. The second signal is generated by the transadmittance amplifier stage based on the gain recovery of the first signal and the high frequency gains of the first signal. The transimpedance amplifier stage is configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.

Abstract translation: 跨导放大器级耦合到跨阻放大器级以形成连续时间线性均衡器。 所述互导体放大器级具有第一和第二增益路径，并且被配置为输入第一信号并输出​​第二信号。 第一增益路径被配置为向第一信号提供DC增益恢复和第一高频增益。 第二增益路径被配置为向第一信号提供第二高频增益。 基于第一信号的增益恢复和第一信号的高频增益，由导纳放大器级产生第二信号。 跨阻放大器级被配置为输入来自跨导纳放大器级的第二信号，并将第二信号转换为输出电压信号。

公开(公告)号：WO2021047370A1

公开(公告)日：2021-03-18

申请号：PCT/CN2020/110331

申请日：2020-08-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre ,  MOHSENPOUR, MohammadMahdi

IPC: H04L7/033

Abstract: The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f 1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f 2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f 1 and the common mode encoding the second high-speed clock frequency f 2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.

公开(公告)号：WO2020094037A1

公开(公告)日：2020-05-14

申请号：PCT/CN2019/115891

申请日：2019-11-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre

IPC: G01R31/01

Abstract: There is provided an integrated loopback used for on-die self-test and diagnosis of transceiver faults. According to embodiments, there is provided an interface network including an AC coupling capacitor interposed between input pins of the interface network and an input of an amplifier, a shunt capacitor interposed between the AC coupling capacitor and the input of the amplifier and a selector. The selector includes a mission mode circuit component connected to a bottom plate of the shunt capacitor and the selector is configured to select between a first mode and a second mode, wherein the first mode is mission mode and the second mode is loopback mode, wherein in the second mode the mission mode circuit component forms at least part of a circuit that supplies a loopback signal.

公开(公告)号：WO2019015483A1

公开(公告)日：2019-01-24

申请号：PCT/CN2018/094688

申请日：2018-07-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： TONIETTO, Davide ,  LACROIX, Marc-Andre ,  WONG, Henry

IPC: H03M13/03 ,  G06F11/07

CPC classification number: H04L1/0045 ,  B64C1/00 ,  F16J15/123 ,  H04L43/0823

Abstract: Methods, systems and computer-readable media for optimizing SerDes system parameters based on a bit error rate detected by a forward error correction unit (FEC). A SerDes receiver receives a data stream over a link and uses a (FEC) to detect error information in the received data stream. The system tunes and optimizes one or more SerDes system parameters using the detected error information. The system minimizes power consumption by decreasing power supply voltage until a maximum acceptable input error rate threshold is reached. The (FEC) allows the system to tolerate errors in the input data stream up to the threshold while preventing propagation of these errors in the (FEC) output data stream.

公开(公告)号：WO2018196620A1

公开(公告)日：2018-11-01

申请号：PCT/CN2018/082765

申请日：2018-04-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre ,  LEBEDEV, Semyon ,  WONG, Henry ,  TONIETTO, Davide

IPC: H03M1/38

Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

公开(公告)号：WO2016112753A1

公开(公告)日：2016-07-21

申请号：PCT/CN2015/096464

申请日：2015-12-04

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LACROIX, Marc-Andre

IPC: H04B1/40

CPC classification number: H04B3/548

Abstract: A front-end of a first differential circuit is DC-coupled to a second differential circuit. The front-end comprises a resistive element, a voltage sensor and a current adjustor. The resistive element has a resistivity between a first end that is DC-coupled to the second circuit and a second end that is DC-coupled to the first circuit and accepts a programmable current passing therethrough to impose a voltage across the element that varies in direction and amplitude according to the current value. The voltage sensor senses a difference between a DC voltage at the second end of the resistive element and a desired reference voltage of the first circuit. The current adjustor adjusts a direction and amplitude of the programmable current so that the voltage of the first circuit matches the desired reference voltage of the first circuit. The first circuit may be a receiver circuit and the second circuit may be a transmitter circuit. The front-end may further comprise a current canceller comprising a second resistive element connected at a first end to the output of the second circuit. The current canceller senses the programmable current and generates a current of equal amplitude through the second resistive element and away from the output of the second circuit. The current canceller may be implemented in digital or analog form and/or in differential or common-mode operation.

Abstract translation: 第一差分电路的前端被直流耦合到第二差分电路。 前端包括电阻元件，电压传感器和电流调节器。 电阻元件在与第二电路直流耦合的第一端和与第一电路直流耦合的第二端之间具有电阻率，并且接受通过其中的可编程电流，从而在方向上变化的元件施加电压 和幅度根据当前值。 电压传感器感测电阻元件的第二端处的直流电压与第一电路的期望参考电压之间的差。 电流调节器调节可编程电流的方向和幅度，使得第一电路的电压与第一电路的期望参考电压匹配。 第一电路可以是接收器电路，第二电路可以是发射机电路。 前端还可以包括电流消除器，其包括在第一端连接到第二电路的输出的第二电阻元件。 电流消除器感测可编程电流并且通过第二电阻元件产生相等振幅的电流并远离第二电路的输出。 电流消除器可以以数字或模拟形式和/或差分或共模操作来实现。

公开(公告)号：WO2022089226A1

公开(公告)日：2022-05-05

申请号：PCT/CN2021/124157

申请日：2021-10-15

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LEBEDEV, Semyon ,  ZAMANLOOY, Babak ,  LACROIX, Marc-Andre

IPC: H03M1/46 ,  H03M1/12

Abstract: Systems and circuits for an asynchronous SAR ADC (300) are described. The SAR ADC (300) includes a two-stage comparator (320) with a preamplifier first stage (322) and a latch second stage (324). The preamplifier first stage (322) is activated by an active pulse of a first clock signal (CLK1B) and the latch second stage (324) is activated by an active pulse of a second clock signal (CLK2). The Done signal from a done detector (340) is fed back as the active pulse of the first clock signal (CLK1B). The leading edge of the active pulse of the second clock signal (CLK2) is driven by the leading edge of the active pulse of the first clock signal (CLK1B) via an RS latch (342).

公开(公告)号：WO2020177643A1

公开(公告)日：2020-09-10

申请号：PCT/CN2020/077310

申请日：2020-02-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： KROTNEV, Petar Ivanov ,  TONIETTO, Davide ,  LACROIX, Marc-Andre

IPC: H04L5/16

Abstract: A method includes deactivating transmitters of a first plurality of transceivers that are associated with an endpoint to multi-channel communication fabric. A given transceiver of the first plurality of transceivers includes a receiver. The method includes controlling the given transceiver to cause the given transceiver to couple a reference source of the given transceiver to a first node of the receiver, measure a first value at a second node of the receiver, and determine a gain between the first node and the second node based on the measured first value. The method includes controlling the given receiver to cause the given receiver to isolate the reference source from the first node of the receiver; and measuring, by the given transceiver, a second value at the second node and determining, by the given transceiver, an intrinsic noise based on the measured second value. The method includes activating the deactivated transmitters; measuring, by the given transceiver, a third value at the second node and determining, by the given transceiver, a composite noise based on the measured third value; and determining, by the given transceiver, a crosstalk noise at the first node of the receiver based on the determined gain, the determined intrinsic noise and the determined composite noise.

公开(公告)号：WO2018141197A1

公开(公告)日：2018-08-09

申请号：PCT/CN2018/072097

申请日：2018-01-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： CHONG, Euhan ,  LEBEDEV, Semyon ,  LACROIX, Marc-Andre

IPC: H03M1/38

Abstract: Systems and circuits for feedback control of an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) are described. An example system includes the asynchronous SAR ADC (100). A timing detector circuit (302) is coupled to the asynchronous SAR ADC (100) to receive one or more internal signals (310) from the asynchronous SAR ADC (100). The timing detector circuit (302) outputs a timing detector signal (312) representing an internal timing of the SAR ADC (100). The timing detector signal (312) is generated based on the one or more internal signals (310). A regulator circuit (304) is coupled to the timing detector circuit (302) to receive the timing detector signal (312). The regulator circuit (304) is also coupled to the asynchronous SAR ADC (100) to output a feedback signal (314) to the asynchronous SAR ADC (100). The feedback signal (314) is generated based on the timing detector signal (312) to control the internal timing of the SAR ADC (100) to match a target timing.