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    CHANNEL ADAPTIVE ITERATIVE TURBO DECODER SYSTEM AND METHOD
    1.
    发明申请
    CHANNEL ADAPTIVE ITERATIVE TURBO DECODER SYSTEM AND METHOD 审中-公开
    通道自适应迭代涡轮解码器系统及方法

    公开(公告)号：WO2010033537A1

    公开(公告)日：2010-03-25

    申请号：PCT/US2009/057079

    申请日：2009-09-16

    Applicant: ANALOG DEVICES, INC. ,  STEIN, Yosef ,  MALEPATI, Hazarathaiah ,  PRIMO, Haim

    Inventor： STEIN, Yosef ,  MALEPATI, Hazarathaiah ,  PRIMO, Haim

    IPC: H03M13/39 ,  H03M13/29

    CPC classification number: H03M13/2957 ,  H03M13/2975 ,  H03M13/3905 ,  H03M13/3927 ,  H03M13/3994 ,  H04L1/005 ,  H04L1/0055 ,  H04L1/0071

    Abstract: A channel adaptive iterative turbo decoder for computing with MAP decoders a set of branch metrics for a window of received data, computing the forward and reverse recursive path state metrics and computing from the forward and reverse recursive path state metrics the log likelihood ratio for 1 and 0 and interleaving the decision bits; and identifying those MAP decoder decision bits which are non-convergent, computing a set of branch metrics for the received data, computing from the forward and reverse recursive path state metrics the log likelihood ratio (LLR) for 1 and 0 for each non-converged decision bit and interleaving the non-convergent decision bits.

    Abstract translation: 一种信道自适应迭代turbo解码器，用于使用MAP解码器计算接收数据窗口的一组分支度量，计算正向和反向递归路径状态度量，以及从正向和反向递归路径状态度量计算1和对数似然比 0并交错判决位; 并且识别那些不收敛的MAP解码器判定比特，计算接收数据的一组分支度量，从正向和反向递归路径状态度量，计算每个非收敛的对数似然比（LLR）1和0 判决位和交织非收敛判定位。

    METRIC CALCULATIONS FOR MAP DECODING USING THE BUTTERFLY STRUCTURE OF THE TRELLIS
    2.
    发明申请
    METRIC CALCULATIONS FOR MAP DECODING USING THE BUTTERFLY STRUCTURE OF THE TRELLIS 审中-公开
    使用TRELLIS的BUTTERFLY结构进行地图解码的公制计算

    公开(公告)号：WO2006092564A8

    公开(公告)日：2007-10-25

    申请号：PCT/GB2006000652

    申请日：2006-02-24

    Applicant: TTP COMMUNICATIONS LTD ,  VALADON CYRIL

    Inventor： VALADON CYRIL

    IPC: H03M13/45

    CPC classification number: H03M13/3927 ,  H03M13/3961

    Abstract: A method of calculating branch metrics for a butterfly in a trellis of a MAP-genre decoding algorithm, the method comprising providing initialised branch metrics for the transitions in the butterfly and incrementing the branch metrics with a group of data values corresponding to said transitions in accordance with control signals derived from the butterfly index and one or more polynomials describing tap positions of the encoding equipment to whose operation the trellis relates, wherein said group comprises systematic bit and parity bit values.

    Abstract translation: 一种在MAP类型解码算法的网格中计算蝴蝶的分支度量的方法，所述方法包括：提供用于蝶形转换的初始化分支度量，并根据对应于所述转换的一组数据值递增分支度量 具有从蝴蝶索引导出的控制信号和一个或多个多项式来描述网格与其操作相关的编码设备的抽头位置，其中所述组包括系统位和奇偶校验位值。

    METHOD AND APPARATUS FOR DECODING OF TURBO ENCODED DATA
    4.
    发明申请
    METHOD AND APPARATUS FOR DECODING OF TURBO ENCODED DATA 审中-公开
    用于解码涡轮编码数据的方法和装置

    公开(公告)号：WO02023739A2

    公开(公告)日：2002-03-21

    申请号：PCT/US2001/028974

    申请日：2001-09-12

    IPC: H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  H03M13/00

    CPC classification number: H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    Abstract: propabad and apparatus for reducing memory requirements and increasing speed of decoding of turbo encoded data in a MAP decoder. Turbo coded data is decoded by computing alpha values and saving checkpoint alpha values on a stack. The checkpoint values are then used to recreate the alpha values to be used in computations when needed. By saving only a subset of the Alpha values memory to hold them is conserved. Alpha and beta computations are made using a min* operation which provides a mathematic equivalence for adding logarithmic values without having to convert from the logarithmic domain. To increase the speed of the min* operation logarithmic values are computed assuming that one min* input is larger than the other and visa versa at the same time. The correct value is selected later based on a partial resulta calculation comparing the values accepted for the min* calculation. Additionally calculations are begun without waiting for previous calculations to finish. The computational values are kept to a minimal accuracy to minimize propagation delay. An offset is added to the logarithmic calculations in order to keep the calculations from becoming negative and requiring another bit to represent a sign bit. Circuits that correct for errors in partial results are employed. Normalization circuits which zero alpha and beta most significant bits based on a previous decoder interation are employed to add only minimal time to circuit critical paths.

    Abstract translation: 推进器和用于减少存储器需求并提高MAP解码器中turbo编码数据解码速度的装置。 Turbo编码数据通过计算alpha值并在堆栈上保存检查点alpha值进行解码。 然后，检查点值用于在需要时重新创建要用于计算的alpha值。 通过仅保存Alpha值的一部分内存来保存它们是保守的。 Alpha和Beta计算使用min *操作进行，该操作为添加对数值提供数学等效性，而无需从对数域转换。 为了提高min *的速度运算，假设一分钟*的输入大于另一个，反之亦然，则计算对数值。 稍后将基于部分结果计算比较最小*计算所接受的值来选择正确的值。 另外计算开始，而不等待以前的计算结束。 计算值保持最小的精度以最小化传播延迟。 将偏移量加到对数计算中，以便使计算不会变为负值，并需要另一个位来表示一个符号位。 采用校正部分结果误差的电路。 采用基于先前的解码器间隔使α和β最高有效位为零的归一化电路仅对电路关键路径增加最小时间。

    PARALLEL CONCATENATED CODE WITH SOFT-IN SOFT-OUT INTERACTIVE TURBO DECODER
    5.
    发明申请
    PARALLEL CONCATENATED CODE WITH SOFT-IN SOFT-OUT INTERACTIVE TURBO DECODER 审中-公开
    带软启动互动式涡轮解码器的并行定义代码

    公开(公告)号：WO02023738A2

    公开(公告)日：2002-03-21

    申请号：PCT/US2001/028875

    申请日：2001-09-12

    IPC: H03M13/15 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29 ,  H03M13/41 ,  H03M13/45 ,  H04L1/00 ,  H03M13/00

    CPC classification number: H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    Abstract: A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder ma have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

    Abstract translation: 一种并行级联（Turbo）编码和解码的方法。 Turbo编码器接收一系列输入数据元组并进行编码。 输入序列可以对应于原始数据源的序列，或者对应于已由Reed-Solomon编码器提供的已经编码的数据序列。 turbo编码器通常包括由一个或多个交织器分离的两个或更多个编码器。 输入数据元组可以使用其中交织根据某些方法（诸如块或随机交织）的加法规则进行交织，其中输入元组只能交织到具有相同模N的交织位置 其中N是整数），因为它们在输入数据序列中具有。 如果所有输入元组由所有编码器编码，则输出元组可以从编码器顺序选择，并且不会丢失元组。 如果输入元组包含多个比特，那么这些比特可以与具有相同模N和相同比特位置的交织位置独立交织。 这可以提高代码的鲁棒性。 第一编码器没有交织器，或者所有编码器可以具有交织器，无论输入元组位是否独立交错。 模式类型交织也允许并行解码。

    TURBO DECODER AND TURBO DECODING METHOD
    6.
    发明申请
    TURBO DECODER AND TURBO DECODING METHOD 审中-公开
    turbo解码器和涡轮decode方法

    公开(公告)号：WO01069788A2

    公开(公告)日：2001-09-20

    申请号：PCT/DE2001/000982

    申请日：2001-03-12

    IPC: H03M13/29 ,  H03M13/45 ,  H04L1/00 ,  H03M

    CPC classification number: H03M13/3905 ,  H03M13/2957 ,  H03M13/3723 ,  H03M13/3927 ,  H03M13/3961 ,  H03M13/6577 ,  H03M13/658

    Abstract: The invention relates to a turbo decoder which is provided for decoding a data signal (D) transmitted over a disturbed channel and which comprises a symbol estimator (MAP_DEC) and a digital signal processor (DSP). Inside a calculating loop of the iterative turbo decoding, the symbol estimator (MAP_DEC) conducts two symbol estimations and the DSP conducts an interleaving procedure and a deinterleaving procedure. A bi-directional interface (FMI) is provided for the transmission of data between the symbol estimator (MAP_DEC) and the DSP.

    Abstract translation: 一种用于解码经由扰的通道数据信号（D）发送的turbo解码器包括符号估计器（MAP_DEC）和数字信号处理器（DSP）。 内的符号估计器（MAP_DEC）两个符号估计和DSP的迭代Turbo解码的计算循环执行锁定和交织过程。 用于符号估算（MAP_DEC）和DSP之间的数据传输是双向接口被提供（FMI）。

    MATRIX BASED PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY (MAP) DECODERS
    8.
    发明申请
    MATRIX BASED PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY (MAP) DECODERS 审中-公开
    基于MATRIX的并行实现最大似然概率（MAP）解码器

    公开(公告)号：WO2013085812A1

    公开(公告)日：2013-06-13

    申请号：PCT/US2012/067283

    申请日：2012-11-30

    Applicant: THE MATHWORKS, INC. ,  FANOUS, Brian ,  STEFANSSON, Halldor N.

    Inventor： FANOUS, Brian ,  STEFANSSON, Halldor N.

    IPC: H03M13/39

    CPC classification number: G06F17/16 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3966 ,  H03M13/616

    Abstract: A MAP decoder may be implemented in parallel on the basis of a matrix based description of the MAP algorithm. In one implementation, a device may receive an input array that represents received encoded data (610) and calculate, in parallel, a series of transition matrices from the input array (620). The device may further calculate, in parallel, products of the cumulative products of the series of transition matrices and an initialization vector (630). The device may further calculate, in parallel and based on the products of the cumulative products of the series of transition matrices and the initialization vector, an output array that corresponds to a decoded version of the received encoded data in the input array (640). The caluclations may be based on the so-called scan technique/scan algorithm. The above approach may allow to implement MAP decoding in technical computing envorinments (TCE) or on GPUs.

    Abstract translation: 可以基于MAP算法的基于矩阵的描述来并行地实现MAP解码器。 在一个实现中，设备可以接收表示接收的编码数据（610）并且并行计算来自输入阵列（620）的一系列转移矩阵的输入阵列。 该装置还可以并行地计算一系列转移矩阵的累积乘积和初始化向量（630）的乘积。 该装置还可以并行地并且基于一系列转移矩阵和初始化向量的累积乘积的乘积计算输出阵列（640）中对应于接收的编码数据的解码版本的输出阵列。 校准可以基于所谓的扫描技术/扫描算法。 上述方法可能允许在技术计算环境（TCE）或GPU上实现MAP解码。

    MESM: A FAST BJCR BASED DECODER IMPLEMENTATION SCHEME
    9.
    发明申请
    MESM: A FAST BJCR BASED DECODER IMPLEMENTATION SCHEME 审中-公开
    MESM：基于快速BJCR的解码器实现方案

    公开(公告)号：WO2009118713A1

    公开(公告)日：2009-10-01

    申请号：PCT/IB2009/051299

    申请日：2009-03-27

    Applicant: NXP B.V. ,  HU, Jianhao ,  LI, Feng ,  WEN, Hong

    Inventor： HU, Jianhao ,  LI, Feng ,  WEN, Hong

    IPC: H03M13/39

    CPC classification number: H03M13/3905 ,  H03M13/3927 ,  H03M13/6505

    Abstract: A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations.

    Abstract translation: 一种基于BCJR的前向纠错算法的存储器高效，加速实现架构。 在这种架构中，采用存储器效率存储方案用于度量和信道信息，以低存储器要求实现高处理速度。 因此，可以加速基于BCJR的算法，并且可以减少实现复杂度。 该方案可用于基于BCJR的turbo解码器和LDPC解码器实现。

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