公开(公告)号：WO2013085575A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/049372

申请日：2012-08-02

Applicant: BATTELLE ENERGY ALLIANCE, LLC

Inventor： MORADI, Hussein ,  BEHROUZ, Farhang ,  KUTSCHE, Carl, A.

IPC: H04B1/00

CPC classification number: H04B1/7093 ,  H04B1/69 ,  H04B1/707 ,  H04B1/709 ,  H04B1/71 ,  H04B2001/70935 ,  H04J11/0023 ,  H04K3/25 ,  H04K3/827 ,  H04L1/04 ,  H04L5/0021 ,  H04L9/0816 ,  H04L9/0875 ,  H04L27/264 ,  H04L2209/24 ,  H04L2209/80 ,  H04W12/04

Abstract: A transmitter includes a synthesis filter bank to spread a data symbol to a plurality of frequencies by encoding the data symbol on each frequency, apply a common pulse-shaping filter, and apply gains to the frequencies such that a power level of each frequency is less than a noise level of other communication signals within the spectrum. Each frequency is modulated onto a different evenly spaced subcarrier. A demodulator in a receiver converts a radio frequency input to a spread-spectrum signal in a baseband. A matched filter filters the spread-spectrum signal with a common filter having characteristics matched to the synthesis filter bank in the transmitter by filtering each frequency to generate a sequence of narrow pulses. A carrier recovery unit generates control signals responsive to the narrow pulses suitable for generating a phase locked loop between the demodulator, the matched filter, and the carrier recovery unit.

Abstract translation: 发射机包括合成滤波器组，用于通过对每个频率上的数据符号进行编码来将数据符号扩展到多个频率，应用公共脉冲整形滤波器，并对频率施加增益，使得每个频率的功率电平较小 比频谱内其他通信信号的噪声水平高。 每个频率被调制到不同的均匀间隔子载波上。 接收机中的解调器将射频输入转换为基带中的扩频信号。 匹配滤波器利用具有与发射机中的合成滤波器组匹配的特性的公共滤波器对扩频信号进行滤波以对每个频率进行滤波以产生窄脉冲序列。 载波恢复单元产生响应于适于在解调器，匹配滤波器和载波恢复单元之间产生锁相环的窄脉冲的控制信号。

公开(公告)号：WO2013041650A1

公开(公告)日：2013-03-28

申请号：PCT/EP2012/068588

申请日：2012-09-21

Applicant: ST-ERICSSON SA ,  NAS, Ricky ,  SMEETS, Jean-Paul ,  VAN BERKEL, Cornelis

Inventor： NAS, Ricky ,  SMEETS, Jean-Paul ,  VAN BERKEL, Cornelis

IPC: H04B1/7115

CPC classification number: H04B1/7115 ,  H04B2001/70935 ,  H04B2201/709727

Abstract: An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, or each spreading code.

Abstract translation: 提供中间符号缓冲器（ISB）配置和方法，使得ISB存储器包括15个部分，每个HSDPA扩展码一个。 与扩展码相关联的符号被写入与相同扩展码相关联的存储器部分。 当执行协方差计算以获得更准确的信道估计时，只有与确定为协方差计算所需的扩展码相关联的符号由缓冲块写入ISB，并且通过相关核心从ISB写入红色。 与协方差计算所不需要的扩展码相关联的符号可以从ISB中被写入或读取。 在一些实施例中，每个存储器部分是单个存储器块。 在其他实施例中，多个存储器块可以包含多个存储器部分，至少暂时指定一个或每个扩展码的一个存储器分区。

公开(公告)号：WO2007102897A3

公开(公告)日：2007-11-29

申请号：PCT/US2006061163

申请日：2006-11-21

Applicant: QUALCOMM INC ,  BANISTER BRIAN CLARKE

Inventor： BANISTER BRIAN CLARKE

IPC: H04B1/707

CPC classification number: H04B1/71075 ,  H04B1/712 ,  H04B2001/70935

Abstract: Techniques for performing interference cancellation in a wireless (eg, CDMA) communication system are described. For a single-sector interference canceller, received samples are processed (e.g., despread) to isolate a signal from a transmitter (e.g., a base station) and obtain input samples. The input samples are transformed based on a first transform (e.g., a fast Hadamard transform) (416) to obtain received symbols for multiple orthogonal channels (e.g., Walsh bins) . The received symbols for the multiple orthogonal channels are scaled with multiple gains (440) to obtain scaled symbols. The gains may be related to the inverses of the power estimates for the orthogonal channels. The scaled symbols are transformed based on a second transform (e.g., an inverse fast Hadamard transform) (442) to obtain output samples, which are processed (e.g., spread) to obtain interference-canceled samples having the signal from the transmitter suppressed.

Abstract translation: 描述了在无线（例如CDMA）通信系统中执行干扰消除的技术。 对于单扇区干扰消除器，接收的样本被处理（例如，去扩展）以隔离来自发射机（例如，基站）的信号并获得输入采样。 基于第一变换（例如，快速Hadamard变换）（416）来变换输入样本，以获得用于多个正交信道（例如沃尔什bin）的接收符号。 多个正交信道的接收符号用多个增益（440）缩放以获得缩放的符号。 增益可能与正交信道的功率估计的逆相关。 基于第二变换（例如，逆快速哈达玛变换）（442）来转换经缩放的符号，以获得被处理（例如扩展）以获得具有来自发射机的信号被抑制的干扰消除样本的输出采样。

公开(公告)号：WO2004088856A3

公开(公告)日：2005-01-27

申请号：PCT/US2004008842

申请日：2004-03-22

Applicant: ARRAYCOMM INC ,  BHORA VEERENDRA ,  ROY PULAKESH ,  BOROS TIBOR

Inventor： BHORA VEERENDRA ,  ROY PULAKESH ,  BOROS TIBOR

IPC: H04B1/707

CPC classification number: H04B1/7093 ,  H04B2001/70935

Abstract: In one embodiment, a Walsh-Hadamard decoder can have a hardware efficient Fast Hadamard Transform ("FHT") engine. In one embodiment, the FHT engine can include an input to receive an input sequence to be decoded into a Walsh-Hadamard codeword. The FHT engine can further include a controller to correlate the received input sequence with a plurality of Walsh- Hadamard codewords using two, add/subtract modules. In one embodiment, the two add/subtract modules operate in parallel.

Abstract translation: 在一个实施例中，沃尔什 - 哈达玛解码器可以具有硬件高效的快速哈达玛变换（“FHT”）引擎。 在一个实施例中，FHT引擎可以包括用于接收要解码为沃尔什 - 哈达玛码字的输入序列的输入。 FHT引擎还可以包括控制器，以使用两个加/减模块将接收的输入序列与多个沃尔什 - 哈达玛码字进行相关。 在一个实施例中，两个加/减模块并行操作。

公开(公告)号：WO03034632A2

公开(公告)日：2003-04-24

申请号：PCT/US0231858

申请日：2002-10-04

Applicant: MOTOROLA INC

Inventor： GURNEY DAVID P ,  KUFFNER STEPHEN L ,  COLLINS TIMOTHY JAMES ,  RACHWALSKI RICHARD STANLEY ,  RAKERS PATRICK L ,  KUHLMAN DOUGLAS A ,  MESSERGES THOMAS S ,  EASTMOND BRUCE C

IPC: H04B1/59 ,  H04B1/707 ,  H04B17/00 ,  H04J13/00 ,  H04L1/00 ,  H04L9/06 ,  H04L12/413 ,  H04L

CPC classification number: H04W16/14 ,  H04B1/7093 ,  H04B17/382 ,  H04B2001/70935 ,  H04J13/0022 ,  H04J13/10 ,  H04L1/0001 ,  H04L12/413 ,  H04W24/00

Abstract: A communications method and device that enables multiple source devices (110, 120, 130) to communicate information to a destination device (100) is disclosed. The information communicated from any source device to the destination device (100) typically takes the form of binary electronic product codes ("EPC") or identification ("ID") information. The preferred embodiment of the invention utilizes the techniques of: data scrambling and descrambling; channel selection and transmission; enabling and disabling group transmissions; correlation; and collision mitigation.

Abstract translation: 公开了一种能够使多个源设备（110,120,130）向目的设备（100）传送信息的通信方法和设备。 从任何源设备传送到目标设备（100）的信息通常采取二进制电子产品代码（“EPC”）或标识（“ID”）信息的形式。 本发明的优选实施例利用以下技术：数据加扰和解扰; 频道选择和传输; 启用和禁用组传输; 相关; 和碰撞缓解。

公开(公告)号：WO0245288A3

公开(公告)日：2003-01-30

申请号：PCT/US0143619

申请日：2001-11-20

Applicant: QUALCOMM INC

Inventor： EASTON KENNETH D ,  BLACK PETER J

IPC: H04B1/707 ,  H04B1/709 ,  H04B1/7093 ,  H04Q7/38

CPC classification number: H04B1/707 ,  H04B1/709 ,  H04B2001/70935

Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameters values. The data processor is operated based on a processing clock having a frequency that is (e.g., then or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. the receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof. The correlator despreads the retrieved segments of digitized samples with corresponding segments of PN despreading sequences to provide correlated samples, which are further processed by the symbol demodulation and combiner to provide processed symbols. The second buffer stores the processed symbols, and can be designed to provide de-interleaving of the processed symbols.

Abstract translation: 接收器单元包括以特定采样率接收和存储数字化样本的第一缓冲器，以及从第一缓冲器检索数字化采样的段并且使用特定参数值集处理检索的段的数据处理器。 数据处理器基于具有比采样率高的（例如，或多次）的频率的处理时钟来操作。 可以通过从第一缓冲器检索和处理数字化样本的多个部分来处理接收信号的多个实例。 接收器单元通常还包括接收和处理发射信号以提供数字化样本的接收机以及为数据处理器分派任务的控制器。 数据处理器可以被设计为包括相关器，符号解调和组合器，第一累加器和第二缓冲器，或其组合。 相关器对所取回的数字化样本段进行解扩，以对应的解扩序列段进行解扩，以提供相关样本，由符号解调和组合器进一步处理，以提供处理后的符号。 第二缓冲器存储经处理的符号，并且可以被设计为提供经处理符号的解交织。

公开(公告)号：WO2007102897A2

公开(公告)日：2007-09-13

申请号：PCT/US2006/061163

申请日：2006-11-21

Applicant: QUALCOMM Incorporated ,  BANISTER, Brian Clarke

Inventor： BANISTER, Brian Clarke

IPC: H04B1/707

CPC classification number: H04B1/71075 ,  H04B1/712 ,  H04B2001/70935

Abstract: Techniques for performing interference cancellation in a wireless ( e.g. , CDMA) communication system are described. For a single-sector interference canceller, received samples are processed ( e.g. , despread) to isolate a signal from a transmitter ( e.g. , a base station) and obtain input samples. The input samples are transformed based on a first transform ( e.g. , a fast Hadamard transform) to obtain received symbols for multiple orthogonal channels ( e.g. , Walsh bins). The received symbols for the multiple orthogonal channels are scaled with multiple gains to obtain scaled symbols. The gains may be related to the inverses of the power estimates for the orthogonal channels. The scaled symbols are transformed based on a second transform ( e.g. , an inverse fast Hadamard transform) to obtain output samples, which are processed ( e.g. , spread) to obtain interference-canceled samples having the signal from the transmitter suppressed.

Abstract translation: 描述了在无线（例如CDMA）通信系统中执行干扰消除的技术。 对于单扇区干扰消除器，接收的样本被处理（例如，去扩展）以隔离来自发射机（例如，基站）的信号并获得输入采样。 基于第一变换（例如，快速Hadamard变换）来变换输入样本，以获得用于多个正交信道（例如沃尔什bin）的接收符号。 多个正交信道的接收符号用多个增益进行缩放以获得缩放的符号。 增益可能与正交信道的功率估计的逆相关。 基于第二变换（例如，逆快速哈达马变换）来对经缩放的符号进行变换，以获得处理（例如，扩展）的输出采样，以获得具有来自发送器的信号被抑制的干扰消除样本。

公开(公告)号：WO2005006583A1

公开(公告)日：2005-01-20

申请号：PCT/JP2004/009737

申请日：2004-07-08

Applicant: 末広直樹

Inventor： 末広直樹

IPC: H04B1/707

CPC classification number: H04B1/7075 ,  H04B2001/70935

Abstract: 　符号相関検出が確実にできる信号処理を提供する。 （ａ）は、例えば、８チップ，６４個の複素Ｅ系列符号による信号を処理する場合を示している。（ｂ）は、前処理部３８２における処理を示している。前処理部３８２では、入力した信号Ｘｉに相補関係にある信号Ｙｉを付加する。前処理を行なった信号は、（ｃ）に示すように、相関検出部３８４において、前処理した信号をそれぞれ、６４個用意した整合フィルタ（マッチトフィルタ）３０１～３６４に入力して、どこのフィルタで一致が検出されたかを比較回路３７０で検出している。

Abstract translation: 用于确保检测代码相关性的信号处理。 标号（a）示出了处理例如八个码片和64个复合E序列码的信号的情况。 标号（b）示出了预处理部分（382）中的与输入信号（Xi）相关的信号（Yi）被添加到输入信号（Xi）的处理。 如标号（c）所示，在相关检测部分（384）中，预处理信号被输入到64个匹配滤波器（301-364）中的每一个，比较器电路（370）确定哪个滤波器检测到一致 。

公开(公告)号：WO2004040784A2

公开(公告)日：2004-05-13

申请号：PCT/US2003/035434

申请日：2003-10-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ECKHARDT, Uwe ,  SACHSE, Eric ,  KUHN, Ingo

IPC: H04B1/00

CPC classification number: H04B1/708 ,  H04B1/7093 ,  H04B2001/70935 ,  H04J13/0048 ,  H04L23/02

Abstract: A complementary code decoder technique is provided where the encoded input data is first parallelized. From the parallelized data, correlation values are generated by a correlator circuit that is capable of changing its correlation characteristics depending on at least one control signal. Different control signals are sequentially provided to the correlator circuit thereby driving the correlator circuit to sequentially generate multiple correlation values from the parallelized data, based on different correlation characteristics. From the multiple correlation values, the correlation value that represents the optimum correlation is identified. This technique significantly reduces the gate count of the decoder structure, thus saving chip area and manufacturing costs.

Abstract translation: 提供了一种补码解码器技术，其中编码的输入数据首先被并行化。 根据并行数据，相关值由相关器电路产生，该相关器电路能够根据至少一个控制信号改变其相关特性。 根据不同的相关特性，不同的控制信号被顺序地提供给相关器电路，从而驱动相关器电路从并行数据顺序地生成多个相关值。 从多个相关值中，识别表示最佳相关性的相关值。 这种技术大大减少了解码器结构的门数，从而节省了芯片面积和制造成本。

公开(公告)号：WO2003098812A2

公开(公告)日：2003-11-27

申请号：PCT/IB2003/001516

申请日：2003-04-23

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON

Inventor： BOTTOMLEY, Gregory ,  KHAYRALLAH, Ali

IPC: H04B

CPC classification number: H04B1/7115 ,  H04B1/7117 ,  H04B2001/70935 ,  H04B2201/70705 ,  H04B2201/70707 ,  H04B2201/709727 ,  H04J13/0048

Abstract: A flexible Fast Walsh Transform circuit provides configurable FWT sizes, and is suitable for use in radio receivers where the received signal may be generated using varying spreading codes and/or varying numbers of multi-codes. Such signal types are commonly encountered in wireless communication systems like those based on the Wideband CDMA (W-CDMA) or IS-2000 (cdma2000) standards, and particularly with the higher data rate provisions of those standards. In one application, a RAKE receiver includes RAKE fingers that each include one of the flexible FWT circuits, such that each finger despreads the received signal using variably sized FWTs in accordance with the characteristics of the received signal. The flexibility in FWT sizing may derive from, for example, the inclusion of separately selectable but differently sized FWT circuits, or from the inclusion of a configurable FWT circuit capable of generating different sizes of FWTs.

Abstract translation: 灵活的快速沃尔什变换电路提供可配置的FWT大小，并且适用于无线电接收机，其中接收信号可以使用变化的扩展码和/或不同数量的多码来产生。 在诸如基于宽带CDMA（W-CDMA）或IS-2000（cdma2000）标准的无线通信系统中通常遇到这样的信号类型，特别是在这些标准的较高数据速率规定中。 在一个应用中，RAKE接收机包括RAKE指，其中每个包括柔性FWT电路之一，使得每个指根据接收信号的特性使用可变大小的FWT来解扩接收信号。 FWT尺寸的灵活性可以来自例如包括单独可选择但不同尺寸的FWT电路，或者包括能够产生不同大小的FWT的可配置FWT电路。