公开(公告)号：WO2022011153A8

公开(公告)日：2022-01-13

申请号：PCT/US2021/040909

申请日：2021-07-08

Applicant: NUMEM INC. ,  HALL, Eric ,  SMITH, Doug ,  HENDRICKSON, Nicholas T. ,  GUEDJ, Jack

Inventor： HALL, Eric ,  SMITH, Doug ,  HENDRICKSON, Nicholas T. ,  GUEDJ, Jack

IPC: G06F12/00 ,  G11C11/1697 ,  G11C11/2297 ,  G11C11/54 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0038 ,  G11C2029/1206 ,  G11C2029/3602 ,  G11C2207/2227 ,  G11C2213/35 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/10 ,  G11C29/12 ,  G11C29/16 ,  G11C5/025 ,  G11C7/1006 ,  G11C7/22

Abstract: Systems, methods and devices are disclosed for a smart compute memory circuitry that has the flexibility to perform a wide range of functions inside the memory via logic circuitry and an integrated processor. In one embodiment, the smart compute memory circuitry comprises an integrated processor and logic circuitry to enable adaptive System on a Chip (SOC) and electronics subsystem power or performance improvements, and adaptive memory management and control for the smart compute memory circuitry. A resistive memory array is coupled to the integrated processor. An adaptive memory management and control circuitry (AMMC) to provide extended test, performance, and power optimizing capabilities for a resistive memory is disclosed herein. In one embodiment, a resistive memory comprises a resistive memory array and an Adaptive Memory Management and Control circuitry (AMMC). The AMMC is configured with extended test, reliability, performance and power optimizing capabilities for the resistive memory.

公开(公告)号：WO2020240226A8

公开(公告)日：2020-12-03

申请号：PCT/IB2019/000451

申请日：2019-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TROIA, Alberto ,  MONDELLO, Antonino

IPC: G11C29/16 ,  G11C16/34 ,  G11C29/02 ,  G11C29/04 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G11C16/349 ,  G11C2029/0409 ,  G11C29/021 ,  G11C29/028

Abstract: The present disclosure relates to method for checking the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprises: storing in a dummy row associated to said memory block at least internal block variables and a known pattern; performing a reading of said dummy row; comparing a result of the reading with the known pattern; trimming the parameters of the reading and/or swapping the used memory block based on the result of the comparing.

公开(公告)号：WO2022005517A1

公开(公告)日：2022-01-06

申请号：PCT/US2020/066898

申请日：2020-12-23

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： GOODE, Jonas ,  GALBRAITH, Richard ,  YIP, Henry ,  ALROD, Idan ,  SHARON, Eran

IPC: G11C11/56 ,  G06F11/07 ,  G11C16/34 ,  G11C7/10 ,  G11C29/50 ,  G06F11/1048 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C7/14

Abstract: Dual sense bin balancing (DSBB) to adjust a read level between memory states of an array of NAND flash memory cells implemented in a logic circuit of a NAND flash die or in a storage device controller. Reading a randomized data pattern stored in an array of memory cells includes performing one or more iterations of a DSBB to provide a read level. Each iteration of the DSBB includes performing a first sense read, performing a second sense read, determining a read error, and adjusting the initial read level. The first sense read is performed at a first offset of an initial read level of memory cells to determine a first number of memory cells relative to the first offset. The second sense read is performed at a second offset of the initial read level of memory cells to determine a second number of memory cells relative to the second offset. A read error of the initial read level is determined from the first sense read and the second sense read. The initial read level is adjusted by the read error to provide an adjusted read level. A read of the randomized data pattern is conducted with the read level of the adjusted read level of a last iteration of the DSBB.

公开(公告)号：WO2021126885A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/065167

申请日：2020-12-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEON, Seungjune ,  ZHOU, Zhenming ,  SHEN, Zhenlei

IPC: G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G06F11/10 ,  G06F12/02 ,  G06F9/30101 ,  G11C16/10 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

Abstract: A request to read data at the memory device is received. A first read operation is performed to read the data at the memory device using a first read threshold voltage. The data read at the memory device using the first read threshold voltage is determined to be associated with a first unsuccessful correction of an error. Responsive to determining that the data read at the memory device using the first read threshold voltage is associated with the first unsuccessful correction of the error, a second read threshold voltage is stored at a register to replace a preread threshold voltage previously stored at the register that is associated with the memory device. The first preread threshold voltage was previously used to perform a preread operation at the memory device. A second read operation to read the data at the memory device is performed using the second read threshold voltage.

公开(公告)号：WO2020159628A2

公开(公告)日：2020-08-06

申请号：PCT/US2019/065858

申请日：2019-12-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： SPICA, Michael R. ,  CARAHER, Patrick T.

IPC: G11C5/14 ,  G06F1/3225 ,  G06F3/06 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/3037 ,  G06F11/3058 ,  G06F2201/81 ,  G11C29/021 ,  G11C29/028 ,  G11C5/147

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.